Stars
LLM serving cluster simulator
Repository to host and maintain scale-sim-v2 code
A multi-queue buffer with dynamic buffer space allocation and its Formal Verification TB
A macOS app to view Spaces / Virtual Desktops in the menu bar
MambaOut: Do We Really Need Mamba for Vision? (CVPR 2025)
Virtualized Accelerator Orchestration for Multi-Tenant Workloads
Altera Advanced Synthesis Cookbook 11.0
Haskell to VHDL/Verilog/SystemVerilog compiler
SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course
A scalable High-Level Synthesis framework on MLIR
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
Verilog implementation of Mersenne Twister PRNG
Advanced Interface Bus (AIB) die-to-die hardware open source
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
RTL code of some arbitration algorithm