This project consists of two programs, aiglec and aigviz. The first can fast check the logical equivalence between 2 small combinational AIGs using Reduced Ordered Binary Decision Diagrams (BDDs). The second generates graphical visualization for an AIG and its associated BDD. AIGs with latches (sequential circuits) are not supported.
The AIG files must be in the AIGER format (binary or ASCII).
GraphViz is needed to generate graphical visualization. You will also need g++ and make to compile the source code. To install them in a computer with Ubuntu, open a terminal and type:
sudo apt-get install graphviz g++ make
- Clone the project in your computer:
git clone https://github.com/rafaelcalcada/aigbdd.git
- Open the project directory and build
aiglecandaigvizrunningmake:
cd ./aigbdd
make
- The programs are now ready to use.
To check the logical equivalence between 2 distinct AIGs, type:
./aiglec [aig-file-1] [aig-file-2]
You can generate graphical visualization for both AIGs (and their associated BDDs) appending -v in the command line. For example:
./aiglec graph/test1.aag graph/test2.aag -v
If you're only interested in generating graphical visualization for an AIG, use aigviz:
./aigviz [aig-file]
Distributed under the MIT License. See LICENSE.md for more information.
Rafael Calçada - rafaelcalcada@gmail.com
Project Link: https://github.com/rafaelcalcada/aigbdd
This work was done under the orientation of Professor André Reis as the final work of his Logic Synthesis course. He gave valuable lessons about logic synthesis algorithms.
I also thank my colleague Francisco Knebel for the tips on how to make a decent README page.