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v0.8.0

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Learn about vigilant mode 
Merge rust-embedded#102

102: Prepare v0.8.0 release r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

v0.7.0

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Learn about vigilant mode 
Merge rust-embedded#84

84: bump version to v0.7.0 r=Disasm a=almindor



Co-authored-by: Ales Katona <ales@katona.me>

v0.6.0

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Learn about vigilant mode 
Merge rust-embedded#51

51: Fix {S,U}tvec::trap_mode() functions to match Mtvec::trap_mode() r=almindor a=Disasm

See also: rust-embedded#50 (comment)

Co-authored-by: Vadim Kaushan <admin@disasm.info>

v0.5.6

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Learn about vigilant mode 
Merge rust-embedded#38

38: Release v0.5.6 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

v0.5.5

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Learn about vigilant mode 
Merge rust-embedded#36

36: Release v0.5.5 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

v0.5.4

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Merge rust-embedded#31

31: Add more CSRs r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

v0.5.3

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Merge rust-embedded#28

28: Add marchid, mhartid and mimpid registers r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

v0.5.2

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Disasm Vadim Kaushan
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Learn about vigilant mode 
Bump version (0.5.2)

v0.5.1

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Bump version (0.5.1)

v0.5.0

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Merge #21

21: Add 64-bit targets, reads for composite CSRs, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
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