Stars
Test suite designed to check compliance with the SystemVerilog standard.
Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…
Your definitive source for dashboard icons.
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.
Xilinx Embedded Software (embeddedsw) Development
Runtime-First FPGA Interchange Routing Contest @ FPGA’24
Quickly find differences and similarities in disassembled code
Python bindings for slang, a library for compiling SystemVerilog
Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …
Determines the modules declared and instantiated in a SystemVerilog file
Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
Rich is a Python library for rich text and beautiful formatting in the terminal.
A utility-first CSS framework for rapid UI development.
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Cyclone V bitstream reverse-engineering project
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Tool for shell commands execution, visualization and alerting. Configured with a simple YAML file.
Python script to transform a VCD file to wavedrom format