Tags: roman3017/SpinalHDL
Tags
v1.2.0 : HardType update Instead of passing hardware datatype arguements as [T <: Data](dataType : T) and then using cloneOf(dataType), please use [T <: Data](dataType : HardType[T]) and then dataType() It is safer as it remove the usage of the cloneOf and also avoid instanciating a signal into the netlist just for generation purposes. - Add anonymSignalUniqueness feature SpinalHDL#144 - Literals are now propagated over one basetype - Fix expression ScalaLocated trigger - Better bit access error reporting - Mem/Vec/Flow/Stream are now using HardType instead of cloneOf(signal) - Hardtype don't instanciate stuff unless it's required - missing unsetRegIfNoAssignementTag now emit a warning instead of a error - Add parameter rtlHeader in SpinalConfig, use to generate a custom header in the rtl file generated - Add bit vectors casting with specific width - Add SpiDdr - Add FlowMonitor - Fix missing attribut postfix on ram - Add a _ postfix in verilog on signals with duplicated names SpinalHDL#133 - Fix non deterministic generation - Add SpinalSystemVerilog (emit assertion in a SV way) - Add extra flags option to verilator command - Add `ifndef SYNTHESIS ... `endif around $display - Typo enum encoding Sequancial -> Sequential - fix SpinalHDL#134 literal bit width 8000 - verilog module's output which are internaly read doesn't generate an intermediat signal anymore - Better Nameable priority control, add RegNext and Delay regs name - fix Qsysify - Fix Apb3Decoder lock on unmapped access - fix mem blackboxing
v1.1.6 - ClockDomainTag can now be used to enforce clock domain checking on blackbox IO - Fix Bug: resizeLeft() SpinalHDL#123 - Fix prefix length for inlineRom (Verilog) - Fix statemachine stateNext override - Fix std_ulogic with blackbox - Fix I2cCtrl
v0.11.6 - ClockDomainTag can now be used to enforce clock domain checking on blackbox IO - Fix Bug: resizeLeft() SpinalHDL#123 - Fix prefix length for inlineRom (Verilog) - Fix statemachine stateNext override - Fix std_ulogic with blackbox - Fix I2cCtrl
v1.1.3 SpinalHDL : - Verilog is now emiting ROM via the verilog memreadb macro - You can keep the verilog inline rom via the inlineRom flag in SpinalConfig - Workaround a VCS 2017 verilog shift issue SpinalSim : - add simulation phase API - add SpinalSim retain/release feature - Add experimental simulation tools for stream - Add SimData
v1,1,2 - Fix uart decoder boot conditions - Verilator now split files into chunks of 4000 lines to have a faster compilation on big designs - Now the crossclocking check will also walk the clocks paths to see if two clock domains share the same common driver - Add simPublic feature, which allow to read internal signals of the Dut during simulations - MaskedLiteral are can no be compared to each other (usefull for hashmap) - SwitchStatement elements are now able to properly give their code location - Flip a direction less signal now produce a PendingError instead of a SpinalError (Easier to debug) - removing the need for `.` in `.elsewhen`(Thanks soronpo) - SpinalSim run on Mac - Fix assignement overriding detection - SpinalSim add abstract randomize / assignBigInt
v1.1.1 - Fix SpinalSim simulation model (how it manage sensitivity, threads, backend evaluation, commands to write duts signals), this could break some of your testbench (clockdomain.waitUntilXX is now behaving exactly like the equivalent in VHDL/Verilog. In previous version, it was waiting one additional delta cycles) - SpinalSim is now supported in windows - Add SimTimeout - Add Verilator model optimisation flag - Catch Verilator flow exceptions - Better clock crossing error reporting
v1.1.0
- Rework SimConfig API to allow building custom reusable configurations : SimConfig.withWave.compile(new Dut).doSim{ dut => }
- Refractoring of doManagedSim into doSim
- Add simSuccess, simfailure
- Add clockDomain.waitSampling
- Add clockDomain.forkSimSpeedPrinter
- Add doSimUntilVoid
- Fix sim waves and workspace naming collision checking
- Fix sim workspace colision detection
- Verilator compile with -j2 now
v1.0.5 - *You need to add fork := true into your build.sbt if you want to run tests from sbt command lines* - Now simulation files are emited in the simWorkspace folder by default - You can override the simWorkspace path by setting the SPINALSIM_WORKSPACE environement variable - Clean the why how simulations files are organized - add sim signal.randomize() - Now the VHDL and Verilog backend split long expressions on a multiple assignement. (max 32 expressions per assignement) - Sim waitUntilRisingEdge(count = 100) - SpinalConfig(verbose = true) to print phase timings - Add sim ClockDomain.waitActiveEdgeWhere(cond) - VerilatorBackend now use JNI instread of JNR-FFI to remove a memory leak (it also reduce jar dependancies) - Reduce emited symboles from the Verilator shared object (fix crash when running multiple test from different hardware durring a single VM execution) - SpinalSim is now ready to run multiples tests in multiple threads with multiples hardwares at the same time - Sim API fix toInt (now will return a Int instead than a Long)