Tags: roman3017/SpinalHDL
Tags
v1.3.8: - add SInt/UInt fixpoint and other usefull method extensions - Fix StateMachine onEntry onExit ordering - JtagTap fix bypass register to allow multiple tap on the chain - BufferCC now get a composite name - add spinal.lib.sim.SparseMemory - Fix PLIC with no interrupts - Apb generators now use Handle for address - Axi4 simulation agent now allow to specify read data - Add Simple BmbToAxi4Bridge - Add AS4C32M16SB timings - SdramXdr allow generation without RESETn feature - Update DDR2 software - Add SdramXdr DDR2 simulations (PASS) - Add MT47H64M16HR layout - Add SdramXdr DDR2 layout - XilinxS7Phy now allow burstlength of 4 - sdram XDR replace BL by ctrlBurstLength - Improve SDRAM timings by generations - sdramModel checkers path fix - Fix tasker multi port active to precharge timings - Add Ecp5Sdrx2Phy - Add ECP5 io blackboxes - fix BmbDecoder - Got SdramXdr inferedSdrPhy to work on hardware - Allow BmbDecoder to manage rsp even if cmd didn't fire - Add ECP5 io blackbox - Add KeepAttribute tooling - Now Both VHDL and Verilog backend emit syncronus reads as don't care readDurrinWrite using separated process for each memory ports. - Add Device.ALTERA, which automaticaly add no_rw_check on don'tcare memories - fix SpinalHDL#243 - Fix SpiXdrMasterCtrl full duplex idle MOSI stay now high when idle for better SPI spec compliance - got Xdr Sdram controller to pass SDR model checks - Add Artix 7 STARTUPE2 blackbox - Fix Xdr BmbAdapter refresh handeling - Improve Xdr tester - Fix Xdr backend rsp fifo size - Fix SdramXdr CKE - sdramXdr now use different phases for different commands - Add XdrSdram cocotb model checker - Add Axi arbiter routeBufferM2sPipe - Add lowlatency fifo regressions - SpinalSim allow output clock - Axi arbiters add routeBuffer latency and s2mPipe option - SdramXdr controller stuff fixed, need to improve Tasker timings - Add Smaller and SmallerOrEqual symplifyNode implementation - Add RtlPhy which can be infered by verilator for fast and flexible sim of the XdrSdram controller - Add Stream.repeat - Add sbt-assembly - Add RISC-V machine timer - Add Apb3Monitor/listener - Add Apb3Dummy, usefull to scope APB stuff in simulation - SpinalSim forkStimulus ASYNC now behave as SYNC - add Clock.sync - VerilatorBackend add -Wno-CMPCONST - Fix SpiXdrMasterCtrl without SS - Ram_1wrs now support mask 10000 ed writes - SpiXdrMasterCtrl always give a reset value to ss.activeHigh - Improve StreamFifoCc frequency - Add Axi4CC - Add Axi4Checker - Axi4SharedOnChipRamMultiPort do not support backpresure - Fix artix synthesis bench - add Stream.combStage - Add Axi4Upsizer - Allow HexTools.initRam to work non none 32 bits ram - Fix axi crossbar generation - add AxiReadOnly simulation agents - Axi4 upsized done and tested for INCR burst only - Add spiXdrMasterCtrl pipelining option - Fix Axidecoder when only used with one slave without decodingerror possibility - Merge branch 'blackBoxAsComponent' into dev - allow BB to be emited as regular component - Add Axi4 upsizer, only for INCR bursts - Fix Generator clockdomain - Fix Handle get on lazy default - Now each Generator has its own Handle[ClockDomain] - Add Apb3CC alternative - Fix flow m2sPipe holdPayload
v1.3.4 Fix SpinalHDL#206, Add width assertion on Bool.assignFromBits Fix component substitution due to Component case classes equality checks Fix Data.pull name propagation Ahb mask generation : fix Verilator lint complaints Ahb crossbar allow address downsizing Add Axi4 low latency option Fix some Axi4 crossbar config issues Add Apb3InterruptCtrl
v1.3.3 Fix BusSlaveFactory double underscore name generation Blackbox - Add default value of the generic in the definition of the entity in VHDL Add B(Seq[Bool]) cast Fix Nameable reflect name for componentless stuff Fix switch statements no triggering the scala location collection
v1.3.2 - Fix Verilog EnumPoison values - Avoid VHDL enum literal name clash - SpinalSim do an final sleep(1) after simulation crash to save signals state into the netlist - Remove some useless fork from SpinalSim utiles - PipelinedMemoryBusInterconnect allow adding a master without connection - Add some Mem multi port stream read utiles - Improve SimData and the ScoreboardInOrder API - Improve StreamMonitor/FlowMonitor simulation speed - dockerize - Fix wishbone decoder - Fix Wishbone arbiter bug (same as Decoder) - change some setCompositeName usage to weak - Add BusSlaveFactory.read(address, bitId -> xxx, ...) - Vec.read now unfixWidth to allow variable bit widths - Fix Data.clone ast cleaning - Add readLimit into Prescaler.driveFrom - SpinalSim UartDecoder now avoid printing \r - Fix backend when they have to generate a writeFirst Mem.syncRead. (Not it throw an error instead of generating broken VHDL/Verilog - Fix SpinalHDL#198 (broken addTags) - Improve signal naming (and avoid Vec index name spreading)
v1.3.1 - Add SpinalConfig.randBootFixValue to randomize or not the signals set with randBoot() - Bundle created from HardTypes now keep a reference to him for future clones - Fix library eviction messages SpinalHDL#171 - For each enum signal in the generated verilog there is now a string signal to get a waveform friendly state value. - Simulation ClockDomain.forkStimulus return Unit now - Improve SpinalSim performance by remove debugging asserts - workaround cadence incisive 15.20 VHDL bug (not expression) - Add Data.as(anotherType) casting - Fix AXI4 incr address for unaligned accesses - Add SpinalConfig.withPrivateNamespace feature (toplevel's children components get the toplevel definition name as prefix) - deprecate kB, MB, .. to KiB, MiB - Fix AvalonMMSlaveFactory
v1.3.0 is there !
This update improve SpinalSim by getting ride of the Scala continuation (which were providing the threading/corroutine @suspendable stuff) by replacing it with native JVM threads and adding a thread-less API for simulation speed sensitive things.
This doesn't break backward compatiblity and provide the following advantages :
- No more weird compilation errors related to Scala continuation
- You can now use all the scala syntax into you testbench (For instance for loop wasn't possible by the past inside suspendables)
- No more dependancies to Scala continuation (dying plugin ?)
- The thread-less API is even faster than scala continuation (clockDomain.onSampling{ ... }, ...)
The down sides are :
- The threaded API is now slower, count around 3 us for each thread resume + suspend
- use more memory as each simulation thread use a JVM thread
Also, the SpinalDoc is migrating to readTheDoc.
- Upgrade to sbt 1.2.7 and Scala 2.11.12.
- You can now use SpinalHDL and all the template projects with JDK >= 1.8
- Add simDeltaCycle access function + example
- SpinalSim Add forkSensitiveWhile primitive
- SpinalSim don't use anymore @suspendable stuff as now you can use regular scala for loop
- Add wishbone support with BusSlaveFactory, Arbiter, Decoder, Interconnect, Spi, Uart, ...
- add TriStateArray indexing (return Tristate(Bool))
- Implement ClockDomain.clockEnableDivisionRate (SpinalHDL#166)
- Prohibit BusSlaveFactory to assign reads to the same bit more than once
- Rework SimManger to schedule calls instead of SimThreads
- Add Verilator 4.0 fst wave support (.withFstWave), not the default, can be slower than vcd file
- Add Ice40 blackbox into SpinalLib
- Improve StreamFifo for depth <= 1
- Add flush into Stream.m2sPipe
- SpinalSim UartDecoder now print messages on frame errors
- Implemented assertion that double-read on the same address is not possible (BusSlaveFactory).
- PipelinedMemoryBus interconnect now use raw setCompositeName
- Improve ClockDomain.simSpeedPrinter perf
- Add more composite naming inside the spinal.lib
- Add SpiXdrMasterCtrl with XIP support
- Allow Reg(Bool) init(Boolean)
- SpinalSim add thread-less primitives
- SpinalSim add rtl path option to include third party verilog IP into the verilog compilation
- Grap HexTools from VexRiscv
- fix Bits() with unconstrained bit width
v1.2.2 - Better nameables composition - Add Ahb feature + fix issue wit AhbLite3ToApb3Bridge + verify overlaping for decoder - Remove toAhbLite3Master function in AhbLite3 - Add a new option noAssert in SpinalConfig to disalbe all assert - Add BRAM interface - MuxOH with only two inputs optimisation - Improve OHMasking combinatorial path - Merge branch 'dev' of https://github.com/SpinalHDL/SpinalHDL into dev - remove assert for SizeMapping + update DefaultAhbLite3Slave regarding to the spec - (AhbLite3Decoder) Add the possibility to add a default slave - Merge branch 'dev' of https://github.com/SpinalHDL/SpinalHDL into dev - Fix bus when error occurs in AhbLite3ToApb3Bridge + Add remapAddress function to AhbLite3 - SpinalHDL#137 Add past, changed, stable, rise, fall, initstate formal statements - Add muxListDc (don't care) - Literals with poison values aren't anymore creating assignement overlap - rework formal stuff SpinalHDL#137 - Add CombInit - Add >> << operators to AhbLite3 - Improve AhbLite3Decoder + add function toAhbLiteMaster2 to - AhbLite3 - Add >> << to AhbLite3 - Add noRandBoot feature
PreviousNext