8000 spockman66's list / Hard Project · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content
View spockman66's full-sized avatar
  • Beihang University
  • Beijing

Block or report spockman66

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Stars

Hard Project

9 repositories

LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

SystemVerilog 16 3 Updated May 8, 2024

Xv6 for RISC-V

C 8,012 3,007 Updated Sep 6, 2024

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

SystemVerilog 600 102 Updated Jul 7, 2020

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,540 603 Updated May 16, 2025

VRoom! RISC-V CPU

Verilog 501 26 Updated Sep 2, 2024

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 8,346 638 Updated Aug 18, 2024

A Linux-capable RISC-V multicore for and by the world

SystemVerilog 695 190 Updated Apr 30, 2025

Repository for exercises for Computer Organization and Design: The Hardware/Software Interface 5th Edition

Assembly 334 64 Updated May 2, 2024

ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.

C 2,751 242 Updated May 16, 2025
0