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HW Design Collateral for Caliptra RoT IP
Xiaomi Home Integration for Home Assistant
PCI express simulation framework for Cocotb
PCI express simulation framework for Cocotb
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
Combined library for V2/V3 Inky pHAT and Inky wHAT.
E-Ink Display with a Raspberry Pi and a Web Interface to customize and update the display with various plugins
watch the npu & cpu load of rk3588 chip.观察瑞芯微 RK3588 芯片的 NPU 和 CPU 负载。
Labs for UVM in Cadence Xcelium
Novel GUI Based UVM Testbench Template Builder
OpenTitan: Open source silicon root of trust
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
The official implementation of DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model (ICLR 2025)
Cosmos OpenSSD + Hardware and Software source distribution
Accelerate local LLM inference and finetuning (LLaMA, Mistral, ChatGLM, Qwen, DeepSeek, Mixtral, Gemma, Phi, MiniCPM, Qwen-VL, MiniCPM-V, etc.) on Intel XPU (e.g., local PC with iGPU and NPU, discr…
A textbook on system on chip design using Arm Cortex-A
Collect some IC textbooks for learning.
Simple NVME/SAS/SATA SSD test framework for Linux and Windows
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
A Linux-capable RISC-V multicore for and by the world
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.