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stephenry/README.md

About:

Computer Engineer with advanced proficiency in Logic Design, Computer Architecture and C/C++-based Reference/Architectural Models. My background is as a logic designer but my day to day is writing C++ at a large well-known chip-company. I am based in the UK, but have dual UK-/USA- nationality.

Projects by year

2025

u: Unary-Code Admission Circuits for Arbitrary Vector Lengths (SystemVerilog/C++)

2023

s: Sparse, Fully-Combinatorial Integer Sort Network (SystemVerilog/C++)

2022

v: Key/Value Sorting Design Interview Question Solution (SystemVerilog/C++)

2020

m: Elementary Packet Parser Interview Question Solution (SystemVerilog/C++)

cc: Event-Driven MOESI Cache Coherency Simulator (C++)

ob: High-Performance Order-Book Implementation for FPGA Platforms (SystemVerilog/C++)

pre-2018

qs Microcoded Implementation of the Quicksort Algorithm (SystemVerilog/C++)

WIP

h: High-Performance Key/Value Store (SystemVerilog/C++)

Pinned Loading

  1. h h Public

    A hardware accelerated key/value store.

    SystemVerilog

  2. s s Public

    A single-cycle (S)orter in systemverilog

    SystemVerilog

  3. m m Public

    A solution to a packet parsing design challenge.

    SystemVerilog

  4. v v Public

    A solution to a sorting challenge.

    SystemVerilog

  5. cc cc Public

    A cache coherence simulator for a multiprocessor System On Chip (SOC).

    C++

  6. u u Public

    A collection of efficient circuits to determine if an arbitrary lengthed input vector is a valid unary encoding.

    C++

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