Stars
A powerful Python framework for orchestrating AI agents and managing complex LLM-driven tasks with ease.
This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for EDA.
Verilog evaluation benchmark for large language model
Hey There! Welcome to my journey of dissecting and exploring the corners of Transaction Level Verilog HDL! 100 days of building and experimenting!
AutoGPT is the vision of accessible AI for everyone, to use and to build on. Our mission is to provide the tools, so that you can focus on what matters.
🦜🔗 Build context-aware reasoning applications
A Python based tool for generating hardware registers and their associated files
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
PICSimLab - Programmable IC Simulator Laboratory
Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes
A damn-sexy, open source real-time dashboard builder for IOT and other web mashups. A free open-source alternative to Geckoboard.
Provision remote development environments via Terraform
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
Generate Zynq configurations without using the vendor GUI
iic-jku / IIC-OSIC-TOOLS
Forked from efabless/foss-asic-toolsIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
This repository contain source code for new flow of FreeEDA now know as eSim
A library and command-line tool for querying a Verilog netlist.