Lists (5)
Stars
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Pocket Flow: 100-line LLM framework. Let Agents build Agents!
Pocket Flow: Codebase to Tutorial
Docker-based media server stack featuring Plex, Radarr, Sonarr, and more. Automated downloading, organizing, and streaming with VPN protection and comprehensive monitoring. One-click deployment for…
b4Diary / cores
Forked from ultraembedded/coresVarious HDL (Verilog) IP Cores
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
OpenTitan: Open source silicon root of trust
Fully parametrizable combinatorial parallel LFSR/CRC module
NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching
Processor written in System Verilog. 5 staged piplining, L1 and L2 cache with EWB, tournament branch predictor and BTB
Python based, face detection and tracking example application using VART API.
AltOr32 - Alternative Lightweight OpenRisc CPU
design of a memory sub system with cache memory
pulp_soc is the core building component of PULP based SoCs
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
OpenDLA / OpenDLA
Forked from silicontalks01/OpenDLAA discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Open source FPGA-based NIC and platform for in-network compute
This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 1…
Easy_Eth is a simple ethernet stack based on verilog, support up to 25Gbps. can be implement on Xilinx FPGA and work together with AXI 10G ethernet subsystem IP
Verilog AXI components for FPGA implementation
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.