Lists (1)
Stars
🪐 Modern offline Kanban board app for Windows, MacOS and Linux made with Tauri and Nuxt. Built with simplicity and user experience in mind.
Tools based upon slang for language server purpose
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
System verilog support VS Code Extension
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
System Engineering and requirements management application
A library for interactive command line interfaces in modern C++
Plugins for Yosys developed as part of the F4PGA project.
BS::thread_pool: a fast, lightweight, modern, and easy-to-use C++17 / C++20 / C++23 thread pool library
KLayout technology files for Skywater SKY130
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Modular hardware build system
Verilator open-source SystemVerilog simulator and lint system
SystemVerilog parser library fully compliant with IEEE 1800-2017
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX