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Clocks and PLLs

#282

· sylefeb opened

on Jul 3, 2025

Combinational cycle wrongly detected on array assignement

#277

· Daemiryon opened

on Apr 22, 2025

incorrect verilog code genereted

#276

· Daemiryon opened

on Apr 15, 2025

Enhancement of declaration of and usage of always assignments

#269

· rob-ng15 opened

on Apr 15, 2024

$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */

#268

· FPGAEveryday opened

on Apr 13, 2024

Enhancement of declaration of bram/brom/simple_dualport_bram/dualport_bram

#267

· rob-ng15 opened

on Apr 8, 2024

uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board

#254

· at91rm9200 opened

on Aug 19, 2023

Error initialising bram not brom

#251

· rob-ng15 opened

on May 12, 2023

Unused states that remain and cycles that could be avoided

#248

· sylefeb opened

on Mar 11, 2023

Empty FSM states could be optimized

#247

· suarezvictor opened

on Mar 11, 2023

Many boards share a common set of features, yet each board has its own define

#246

· sylefeb opened

on Mar 5, 2023

pipeline sync

#241

· sylefeb opened

on Feb 12, 2023

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