49 add comment on first line of generated files #50
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Pull Request Overview
This PR ensures that all generated files include a header comment stating they are auto‐generated and should not be edited, while also switching generated file permissions to read-only and bumping the version. Key changes include:
- Inserting header comments based on file extension in RTL, SST simulation, and Bender files.
- Enforcing read-only permissions on generated files.
- Updating the project version and changelog.
Reviewed Changes
Copilot reviewed 8 out of 8 changed files in this pull request and generated 1 comment.
Show a summary per file
| File | Description |
|---|---|
| module/vs-component/src/utils.rs | Adds dynamic comment prefix and header comment insertion in RTL file generation. |
| module/vs-component/src/sst_sim_gen.rs | Prepends the auto-generated header to generated SST configuration files. |
| module/vs-component/src/rtl_code_gen.rs | Incorporates header comment insertion when copying bender files and updates directory copy logic. |
| module/vs-component/src/main.rs | Implements removal of write permissions by invoking new helper logic after file generation. |
| module/vs-component/src/isa_gen.rs | Adjusts ISA JSON generation to include a header comment and uses pretty-printing. |
| module/vs-component/src/drra.rs | Inserts header comments into Bender.yml files during DRRA processing. |
| module/vs-component/Cargo.toml | Bumps the version to 0.2.1. |
| CHANGELOG.md | Updates the changelog to document added header comments and permission changes. |
Comments suppressed due to low confidence (1)
module/vs-component/src/utils.rs:314
- [nitpick] Consider extracting the auto-generated file comment into a constant or helper function to reduce duplication and improve maintainability.
let file_comment = format!("{} This file was automatically generated by Vesyla. DO NOT EDIT.\n\n", comment_prefix);
herenvarno
requested changes
May 6, 2025
herenvarno
approved these changes
May 7, 2025
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Added
[vs-component] Generated files (SystemVerilog, VHDL, JSON and YAML) now have the following comment included (9f71f13):
// This file was automatically generated by Vesyla. DO NOT EDIT.[vs-component] Generated files (SystemVerilog, VHDL, JSON and YAML) permissions are now switched to read-only after file generation (78de714)
Changed