Stars
Rust DataBase Connectivity (RDBC) :: Common Rust API for database drivers
Tigon: A Distributed Database for a CXL Pod [OSDI '25]
Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …
CPU inference for the DeepSeek family of large language models in C++
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs
Allo: A Programming Model for Composable Accelerator Design
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
a high performance library for building cache simulators
PostgreSQL database adapter for the Python programming language
Quick & Flexible Rack-Scale Computer Architecture Simulator
A collection of awesome researchers and papers about disaggregated memory.
zxhero / gem5-CXL
Forked from gem5/gem5This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The…
FPGA synthesis tool powered by program synthesis
An energy-efficient RISC-V floating-point compute cluster.
HammerDB Database Load Testing and Benchmarking Tool
this is a repository based on gem5 and aims to be modified for CXL
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator Based on gem5
A Full-System Simulator for CXL-Based SSD Memory System