slaclab · ruck314 · Jun 20, 2025 · May 16, 2025 · May 17, 2025 · May 19, 2025
diff --git a/axi/axi-lite/rtl/AxiLiteCrossbar.vhd b/axi/axi-lite/rtl/AxiLiteCrossbar.vhd
@@ -123,11 +123,22 @@ architecture rtl of AxiLiteCrossbar is
 
 begin
 
--- synopsys translate_off
    assert (NUM_MASTER_SLOTS_G = MASTERS_CONFIG_G'length)
       report "Mismatch between NUM_MASTER_SLOTS_G and MASTERS_CONFIG_G'length"
-      severity error;
+      severity failure;
+
+   noneZeroCheck : for i in MASTERS_CONFIG_G'range generate
+      assert (MASTERS_CONFIG_G(i).baseAddr(MASTERS_CONFIG_G(i).addrBits-1 downto 0) = 0)
+         report "AXI_LITE_CROSSBAR Configuration Error:" & LF &
+                "  - Array Index       : " & integer'image(i) & LF &
+                "  - baseAddr          : 0x" & hstr(MASTERS_CONFIG_G(i).baseAddr) & LF &
+                "  - addrBits          : " & str(MASTERS_CONFIG_G(i).addrBits) & LF &
+                "  - connectivity      : 0x" & hstr(MASTERS_CONFIG_G(i).connectivity) & LF &
+                "  => baseAddr must be zero within the specified addrBits range."
+         severity failure;
+   end generate noneZeroCheck;
 
+-- synopsys translate_off
    print(DEBUG_G, "AXI_LITE_CROSSBAR: " & LF &
          "NUM_SLAVE_SLOTS_G: " & integer'image(NUM_SLAVE_SLOTS_G) & LF &
          "NUM_MASTER_SLOTS_G: " & integer'image(NUM_MASTER_SLOTS_G) & LF &

diff --git a/axi/axi-lite/rtl/AxiLitePkg.vhd b/axi/axi-lite/rtl/AxiLitePkg.vhd
@@ -1046,7 +1046,7 @@ package body AxiLitePkg is
          & lf & "base     = 0x" & hstr(base)
          & lf & "baseBot  = " & integer'image(baseBot)
          & lf & "addrBits = " & integer'image(addrBits)
-         severity error;
+         severity failure;
 
       -- Check that there is enough bits for the number of buses
       assert (2**(baseBot-addrBits) >= num)
@@ -1055,7 +1055,7 @@ package body AxiLitePkg is
          & lf & "base     = 0x" & hstr(base)
          & lf & "baseBot  = " & integer'image(baseBot)
          & lf & "addrBits = " & integer'image(addrBits)
-         severity error;
+         severity failure;
 
       -------------------------------------------------------------------------------------------
       -- Init

diff --git a/axi/axi-stream/rtl/AxiStreamDeMux.vhd b/axi/axi-stream/rtl/AxiStreamDeMux.vhd
@@ -74,12 +74,12 @@ begin
    assert (MODE_G /= "INDEXED" or (TDEST_HIGH_G - TDEST_LOW_G + 1 >= log2(NUM_MASTERS_G)))
       report "In INDEXED mode, TDest range " & integer'image(TDEST_HIGH_G) & " downto " & integer'image(TDEST_LOW_G) &
       " is too small for NUM_MASTERS_G=" & integer'image(NUM_MASTERS_G)
-      severity error;
+      severity failure;
 
    assert (MODE_G /= "ROUTED" or (TDEST_ROUTES_G'length = NUM_MASTERS_G))
       report "In ROUTED mode, length of TDEST_ROUTES_G: " & integer'image(TDEST_ROUTES_G'length) &
       " must equal NUM_MASTERS_G: " & integer'image(NUM_MASTERS_G)
-      severity error;
+      severity failure;
 
    comb : process (axisRst, dynamicRouteDests, dynamicRouteMasks,
                    pipeAxisSlaves, r, sAxisMaster) is

diff --git a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd
@@ -177,7 +177,7 @@ begin
    assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and
                 SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C))
       report "AxiStreamFifoV2: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side"
-      severity error;
+      severity failure;
 
    -------------------------
    -- Slave Resize

diff --git a/axi/axi-stream/rtl/AxiStreamGearbox.vhd b/axi/axi-stream/rtl/AxiStreamGearbox.vhd
@@ -121,7 +121,7 @@ begin
    assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and
                 SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C))
       report "AxiStreamGearbox: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side"
-      severity error;
+      severity failure;
 
    ---------------------------------------------------------
    -- Use AxiStreamResize if word multiple because less LUTs

diff --git a/axi/axi-stream/rtl/AxiStreamMux.vhd b/axi/axi-stream/rtl/AxiStreamMux.vhd
@@ -115,26 +115,26 @@ begin
 
    assert ((MODE_G = "PASSTHROUGH") or (MODE_G = "INDEXED") or (MODE_G = "ROUTED"))
       report "MODE_G must be either [PASSTHROUGH,INDEXED,ROUTED]"
-      severity error;
+      severity failure;
 
    assert ((MODE_G = "INDEXED") and (7 - TDEST_LOW_G + 1 >= log2(NUM_SLAVES_G))) or (MODE_G /= "INDEXED")
       report "In INDEXED mode, TDest range 7 downto " & integer'image(TDEST_LOW_G) &
       " is too small for NUM_SLAVES_G=" & integer'image(NUM_SLAVES_G)
-      severity error;
+      severity failure;
 
    assert ((MODE_G = "ROUTED") and (TDEST_ROUTES_G'length = NUM_SLAVES_G)) or (MODE_G /= "ROUTED")
       report "In ROUTED mode, length of TDEST_ROUTES_G: " & integer'image(TDEST_ROUTES_G'length) &
       " must equal NUM_SLAVES_G: " & integer'image(NUM_SLAVES_G)
-      severity error;
+      severity failure;
 
    assert ((TID_MODE_G = "PASSTHROUGH") or (TID_MODE_G = "INDEXED") or (TID_MODE_G = "ROUTED"))
       report "TID_MODE_G must be either [PASSTHROUGH,INDEXED,ROUTED]"
-      severity error;
+      severity failure;
 
    assert ((TID_MODE_G = "ROUTED") and (TID_ROUTES_G'length = NUM_SLAVES_G)) or (TID_MODE_G /= "ROUTED")
       report "In ROUTED mode, length of TID_ROUTES_G: " & integer'image(TID_ROUTES_G'length) &
       " must equal NUM_SLAVES_G: " & integer'image(NUM_SLAVES_G)
-      severity error;
+      severity failure;
 
    -- Override TDESTS and TIDs according to the routing tables
    ROUTE_TABLE_REMAP : process (sAxisMasters) is

diff --git a/axi/axi-stream/rtl/AxiStreamResize.vhd b/axi/axi-stream/rtl/AxiStreamResize.vhd
@@ -102,7 +102,7 @@ begin
    assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and
                 SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C))
       report "AxiStreamResize: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side"
-      severity error;
+      severity failure;
 
    comb : process (pipeAxisSlave, r, sAxisMaster, sSideBand) is
       variable v       : RegType;

diff --git a/base/general/rtl/TextUtilPkg.vhd b/base/general/rtl/TextUtilPkg.vhd
@@ -335,7 +335,7 @@ package body TextUtilPkg is
          assert (tmp < base and tmp >= 0) report
             "TextUtilPkg::int(string, integer): Input string (" & s & ") " &
             "has character (" & s(i) & ") outside of base (" & str(base) & ") character set."
-            severity error;
+            severity failure;
          ret := ret * base + tmp;
       end loop;
       return ret;

diff --git a/devices/Amphenol/LeapXcvr/rtl/LeapXcvrCdrDisable.vhd b/devices/Amphenol/LeapXcvr/rtl/LeapXcvrCdrDisable.vhd
@@ -0,0 +1,217 @@
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-------------------------------------------------------------------------------
+-- Description: Used to periodically write CDR disable to the QSFP modules via AXI-Lite crossbar
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiLitePkg.all;
+
+entity LeapXcvrCdrDisable is
+   generic (
+      TPD_G             : time     := 1 ns;
+      PERIODIC_UPDATE_G : positive := 30;  -- Units of seconds
+      LEAP_BASE_ADDR_G  : Slv32Array;  -- List of the LEAP base address offsets
+      AXIL_CLK_FREQ_G   : real);        -- Units of Hz
+   port (
+      -- AXI-Lite Register Interface (axilClk domain)
+      axilClk          : in  sl;
+      axilRst          : in  sl;
+      mAxilReadMaster  : out AxiLiteReadMasterType;
+      mAxilReadSlave   : in  AxiLiteReadSlaveType;
+      mAxilWriteMaster : out AxiLiteWriteMasterType;
+      mAxilWriteSlave  : in  AxiLiteWriteSlaveType);
+end LeapXcvrCdrDisable;
+
+architecture rtl of LeapXcvrCdrDisable is
+
+   constant TIMEOUT_1SEC_C : natural := getTimeRatio(AXIL_CLK_FREQ_G, 1.0);
+
+   constant NUM_CH_G : natural := LEAP_BASE_ADDR_G'length;
+
+   type StateType is (
+      IDLE_S,
+      REQ_S,
+      ACK_S);
+
+   type RegType is record
+      wrd   : natural range 0 to 1;
+      ch    : natural range 0 to NUM_CH_G-1;
+      cnt   : natural range 0 to PERIODIC_UPDATE_G-1;
+      timer : natural range 0 to TIMEOUT_1SEC_C-1;
+      req   : AxiLiteReqType;
+      state : StateType;
+   end record;
+
+   constant REG_INIT_C : RegType := (
+      wrd   => 0,
+      ch    => 0,
+      cnt   => PERIODIC_UPDATE_G-1,
+      timer => TIMEOUT_1SEC_C-1,
+      req   => AXI_LITE_REQ_INIT_C,
+      state => IDLE_S);
+
+   signal r   : RegType := REG_INIT_C;
+   signal rin : RegType;
+
+   signal ack : AxiLiteAckType;
+
+   -- attribute dont_touch        : string;
+   -- attribute dont_touch of r   : signal is "TRUE";
+   -- attribute dont_touch of ack : signal is "TRUE";
+
+begin
+
+   U_AxiLiteMaster : entity surf.AxiLiteMaster
+      generic map (
+         TPD_G => TPD_G)
+      port map (
+         req             => r.req,
+         ack             => ack,
+         axilClk         => axilClk,
+         axilRst         => axilRst,
+         axilWriteMaster => mAxilWriteMaster,
+         axilWriteSlave  => mAxilWriteSlave,
+         axilReadMaster  => mAxilReadMaster,
+         axilReadSlave   => mAxilReadSlave);
+
+   ---------------------
+   -- AXI Lite Interface
+   ---------------------
+   comb : process (ack, axilRst, r) is
+      variable v : RegType;
+   begin
+      -- Latch the current value
+      v := r;
+
+      -- Decrement the timer
+      if (r.timer /= 0) then
+         v.timer := r.timer -1;
+      end if;
+
+      -- State Machine
+      case (r.state) is
+         ----------------------------------------------------------------------
+         when IDLE_S =>
+            -- Check for timeout
+            if (r.timer = 0) then
+
+               -- Re-arm the timer
+               v.timer := TIMEOUT_1SEC_C - 1;
+
+               -- Check for timeout
+               if (r.cnt = 0) then
+
+                  -- Re-arm the counter
+                  v.cnt := PERIODIC_UPDATE_G - 1;
+
+                  -- Next state
+                  v.state := REQ_S;
+
+               else
+                  -- Decrement the counter
+                  v.cnt := r.cnt - 1;
+               end if;
+
+            end if;
+         ----------------------------------------------------------------------
+         when REQ_S =>
+            -- Check if ready for next transaction
+            if (ack.done = '0') then
+
+               -- Setup the AXI-Lite Master request
+               v.req.request := '1';
+               v.req.rnw     := '0';    -- Write operation
+
+               -- Check the word index
+               if (r.wrd = 0) then
+                  v.req.address := LEAP_BASE_ADDR_G(r.ch) + x"0000_00AC";  -- RxLower.GlobalRxCdr=0x0AC
+                  v.req.wrData  := x"0000_0001";  -- Globally turn off all RX CDR channels
+               else
+                  v.req.address := LEAP_BASE_ADDR_G(r.ch) + x"0000_08AC";  -- TxLower.GlobalTxCdr=0x8AC
+                  v.req.wrData  := x"0000_0001";  -- Globally turn off all TX CDR channels
+               end if;
+
+               -- Next state
+               v.state := ACK_S;
+
+            end if;
+         ----------------------------------------------------------------------
+         when ACK_S =>
+            -- Wait for DONE to set
+            if (ack.done = '1') then
+
+               -- Reset the flag
+               v.req.request := '0';
+
+               -- Check if this was last channel
+               if (r.ch = NUM_CH_G-1) then
+
+                  -- Reset the index
+                  v.ch := 0;
+
+                  -- Check the word index
+                  if (r.wrd = 0) then
+
+                     -- Increment the channel
+                     v.wrd := r.wrd + 1;
+
+                     -- Next state
+                     v.state := REQ_S;
+
+                  else
+
+                     -- Reset the index
+                     v.wrd := 0;
+
+                     -- Next state
+                     v.state := IDLE_S;
+
+                  end if;
+
+               else
+
+                  -- Increment the channel
+                  v.ch := r.ch + 1;
+
+                  -- Next state
+                  v.state := REQ_S;
+
+               end if;
+
+            end if;
+      ----------------------------------------------------------------------
+      end case;
+
+      -- Reset
+      if (axilRst = '1') then
+         v := REG_INIT_C;
+      end if;
+
+      -- Register the variable for next clock cycle
+      rin <= v;
+
+   end process comb;
+
+   seq : process (axilClk) is
+   begin
+      if (rising_edge(axilClk)) then
+         r <= rin after TPD_G;
+      end if;
+   end process seq;
+
+end rtl;
diff --git a/devices/transceivers/rtl/QsfpCdrDisable.vhd b/devices/transceivers/rtl/QsfpCdrDisable.vhd
@@ -91,8 +91,7 @@ begin
    -- AXI Lite Interface
    ---------------------
    comb : process (ack, axilRst, r) is
-      variable v      : RegType;
-      variable regCon : AxiLiteEndPointType;
+      variable v : RegType;
    begin
       -- Latch the current value
       v := r;

diff --git a/dsp/generic/fixed/BoxcarIntegrator.vhd b/dsp/generic/fixed/BoxcarIntegrator.vhd
@@ -145,7 +145,7 @@ begin
          if r.rAddr = r.intCount then
             v.rAddr := (others => '0');
          else
-            v.rAddr := r.rAddr + '1';
+            v.rAddr := r.rAddr + 1;
          end if;
 
          -- Write lags read

diff --git a/dsp/generic/ruckus.tcl b/dsp/generic/ruckus.tcl
@@ -2,7 +2,6 @@
 source $::env(RUCKUS_PROC_TCL)
 
 # Load Source Code
-loadSource -lib surf -dir "$::DIR_PATH/core"  -fileType "VHDL 2008"
 loadSource -lib surf -dir "$::DIR_PATH/fixed" -fileType "VHDL 2008"
 
 # Load Simulation

diff --git a/dsp/generic/core/ComplexFixedPkg.vhd → dsp/xilinx/core/ComplexFixedPkg.vhd b/dsp/generic/core/ComplexFixedPkg.vhd → dsp/xilinx/core/ComplexFixedPkg.vhd
diff --git a/dsp/generic/core/DspPkg.vhd → dsp/xilinx/core/DspPkg.vhd b/dsp/generic/core/DspPkg.vhd → dsp/xilinx/core/DspPkg.vhd
diff --git a/dsp/generic/fixed/CfixedAccumulator.vhd → dsp/xilinx/fixed/CfixedAccumulator.vhd b/dsp/generic/fixed/CfixedAccumulator.vhd → dsp/xilinx/fixed/CfixedAccumulator.vhd
diff --git a/dsp/generic/fixed/CfixedDelay.vhd → dsp/xilinx/fixed/CfixedDelay.vhd b/dsp/generic/fixed/CfixedDelay.vhd → dsp/xilinx/fixed/CfixedDelay.vhd
diff --git a/dsp/generic/fixed/CfixedMult.vhd → dsp/xilinx/fixed/CfixedMult.vhd b/dsp/generic/fixed/CfixedMult.vhd → dsp/xilinx/fixed/CfixedMult.vhd
diff --git a/dsp/generic/fixed/CfixedMultAdd.vhd → dsp/xilinx/fixed/CfixedMultAdd.vhd b/dsp/generic/fixed/CfixedMultAdd.vhd → dsp/xilinx/fixed/CfixedMultAdd.vhd
diff --git a/dsp/generic/fixed/CfixedPreAddMult.vhd → dsp/xilinx/fixed/CfixedPreAddMult.vhd b/dsp/generic/fixed/CfixedPreAddMult.vhd → dsp/xilinx/fixed/CfixedPreAddMult.vhd
diff --git a/dsp/generic/fixed/SfixedAccumulator.vhd → dsp/xilinx/fixed/SfixedAccumulator.vhd b/dsp/generic/fixed/SfixedAccumulator.vhd → dsp/xilinx/fixed/SfixedAccumulator.vhd
diff --git a/dsp/generic/fixed/SfixedDelay.vhd → dsp/xilinx/fixed/SfixedDelay.vhd b/dsp/generic/fixed/SfixedDelay.vhd → dsp/xilinx/fixed/SfixedDelay.vhd
diff --git a/dsp/generic/fixed/SfixedMult.vhd → dsp/xilinx/fixed/SfixedMult.vhd b/dsp/generic/fixed/SfixedMult.vhd → dsp/xilinx/fixed/SfixedMult.vhd
diff --git a/dsp/generic/fixed/SfixedMultAdd.vhd → dsp/xilinx/fixed/SfixedMultAdd.vhd b/dsp/generic/fixed/SfixedMultAdd.vhd → dsp/xilinx/fixed/SfixedMultAdd.vhd
diff --git a/dsp/generic/fixed/SfixedPreAddMultAdd.vhd → dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd b/dsp/generic/fixed/SfixedPreAddMultAdd.vhd → dsp/xilinx/fixed/SfixedPreAddMultAdd.vhd
diff --git a/dsp/generic/fixed/SinCosLut.vhd → dsp/xilinx/fixed/SinCosLut.vhd b/dsp/generic/fixed/SinCosLut.vhd → dsp/xilinx/fixed/SinCosLut.vhd
diff --git a/dsp/generic/fixed/SinCosTaylor.vhd → dsp/xilinx/fixed/SinCosTaylor.vhd b/dsp/generic/fixed/SinCosTaylor.vhd → dsp/xilinx/fixed/SinCosTaylor.vhd
diff --git a/dsp/xilinx/ruckus.tcl b/dsp/xilinx/ruckus.tcl
@@ -2,6 +2,7 @@
 source $::env(RUCKUS_PROC_TCL)
 
 # Load Source Code
+loadSource -lib surf -dir "$::DIR_PATH/core"  -fileType "VHDL 2008"
 loadSource -lib surf -dir "$::DIR_PATH/fixed" -fileType "VHDL 2008"
 loadSource -lib surf -dir "$::DIR_PATH/logic" -fileType "VHDL 2008"
 

diff --git a/dsp/generic/tb/CfixedMultAddTb.vhd → dsp/xilinx/tb/CfixedMultAddTb.vhd b/dsp/generic/tb/CfixedMultAddTb.vhd → dsp/xilinx/tb/CfixedMultAddTb.vhd
diff --git a/dsp/generic/tb/CfixedPreAddMultTb.vhd → dsp/xilinx/tb/CfixedPreAddMultTb.vhd b/dsp/generic/tb/CfixedPreAddMultTb.vhd → dsp/xilinx/tb/CfixedPreAddMultTb.vhd
diff --git a/dsp/generic/tb/SinCosLutTb.vhd → dsp/xilinx/tb/SinCosLutTb.vhd b/dsp/generic/tb/SinCosLutTb.vhd → dsp/xilinx/tb/SinCosLutTb.vhd