sun20i: set CONFIG_SYS_BOOTM_LEN for RISC-V #2
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The sunxi_egon type used to take no -A argument (because we assume sunxi targets are all ARM). However, as Allwinner D1 appears as the first RISC-V sunxi target, we need to support -A; in addition, as external projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we need to keep compatibility with command line without -A. As the default value of arch in mkimage is not proper (IH_ARCH_PPC instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag field to image parameters to describe whether an architecture is explicitly specified. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel 8000 Holland <samuel@sholland.org>
Refactor some functions in mkimage sunxi_egon type, in order to prepare for adding support for more CPU architectures (e.g. RISC-V). In addition, compatibility for operation w/o specified architecture is kept, in this case the architecture is assumed as ARM. Series-changes: 3 - Factor out an egon_get_arch() function as suggested by Andre Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org>
There's now a sun20i family in sunxi, which uses RISC-V CPU. Add support for making eGON.BT0 image for RISC-V. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org>
As mkimage -T sunxi_egon now gains support for -A parameter, specify the architecture when generating SPL boot image for sunxi. Series-to: sunxi Series-cc: Icenowy Zheng <icenowy@aosc.io> Series-version: 3 Cover-letter: mkimage: sunxi_egon: add riscv support This patchset updates mkimage -T sunxi_egon to be able to generate an eGON.BT0 image for Allwinner RISC-V SoCs (e.g. D1). In addition, to keep the compatibility, it will still consider the architecture to be ARM when no architecture is specified. This v3 is a minor update to Icenowy's patch series, which I have also tested. Since the TOC0 patch series touches the same lines in Makefile.spl, it depends on this series. END Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org>
Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the existing sunxi_egon image type. The secure boot ROM (SBROM) uses a completely different image type, known as TOC0. A TOC0 image is composed of a header and two or more items. One item is the firmware binary. The others form a chain linking the firmware signature to the root-of-trust public key (ROTPK), which has its hash burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256. The pseudo-ASN.1 structure is manually assembled; this is done to work around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0 implementation has been verified to work with the A50, A64, H5, H6, and H616 SBROMs, and it may work with other SoCs. Series-changes: 2 - Moved certificate and key item structures out of sunxi_image.h - Renamed "main" and "item" variables for clarity - Improved error messages, and added a hint about key generation - Added a comment explaining the purpose of the various key files - Mentioned testing this code on A50 in the commit message Series-changes: 3 - Removed TOOLS_LIBCRYPTO selection for sunxi, since most boards do not need it - Added __packed to all new "ABI" structs - Added entry to MAINTAINERS for sunxi tools Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI" is impossible to satisfy. Signed-off-by: Samuel Holland <samuel@sholland.org>
Currently, if the "offset" property is given for an entry, the section's running offset is completely ignored. This causes entries to overlap if the provided offset is less than the size of the entries earlier in the section. Avoid the overlap by only using the provided offset when it is greater than the running offset. The motivation for this change is the rule used by SPL to find U-Boot on sunxi boards: U-Boot starts 32 KiB after the start of SPL, unless SPL is larger than 32 KiB, in which case U-Boot immediately follows SPL. Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that Crust (SCP firmware) has support for H3, we need a FIT image to load it. H3 also needs to load a SoC-specific eGon blob to support CPU 0 hotplug. Let's first enable FIT support before adding extra firmware. Update the binman description to work on either 32-bit or 64-bit SoCs: - Make BL31 optional, since it is not used on 32-bit SoCs (though BL32 may be used in the future). - Explicitly set the minimum offset of the FIT to 32 KiB, since SPL on some boards is still only 24 KiB large even with FIT support enabled. CONFIG_SPL_PAD_TO cannot be used because it is not defined for H616. FIT unlocks more features (signatures, multiple DTBs, etc.), so enable it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs SPL_FIT_IMAGE_TINY. For simplicity, enable that option everywhere. Cover-letter: sunxi: SPL FIT support for 32-bit sunxi SoCs This series makes the necessary changes so 32-bit sunxi SoCs can load additional device trees or firmware from SPL along with U-Boot proper. There was no existing binman entry property that put the FIT at the right offset. The minimum offset is 32k, but this matches neither the SPL size (which is no more than 24k on some SoCs) nor the FIT alignment (which is 512 bytes in practice due to SPL size constraints). So instead of adding a new property, I fixed what is arguably a bug in the offset property -- though this strategy will not work if someone is intentionally creating overlapping entries. END Series-to: sunxi Series-to: sjg Signed-off-by: Samuel Holland <samuel@sholland.org>
Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked when entering monitor mode, this will hang. Plus, CPU 0 cannot fully power itself off anyway. Instead, have it turn FIQs back on and continue servicing SGIs from other cores. Signed-off-by: Samuel Holland <samuel@sholland.org>
Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be written, resuming CPU 0 requires using the "Super Standby" code path in the BROM instead of the hotplug path. This path requires jumping to an eGON image in SRAM. Add support to the build system to generate this eGON image and include it in the FIT, and add code to direct the BROM to its location in SRAM. Since the Super Standby code path in the BROM initializes the CPU and AHB1 clocks to 24 MHz, those registers need to be restored after control passes back to U-Boot. Furthermore, because the BROM lowers the AHB1 clock divider to /1 before switching to the lower-frequency parent, PLL_PERIPH0 must be bypassed to prevent AHB1 from temporarily running at 600 MHz. Otherwise, this locks up the SoC. Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that issues with the BROM have been sorted out, we can implement PSCI system suspend on H3 by delegating to SCP firmware. Let's start by including the firmware in the FIT image and starting the coprocessor if valid firmware is loaded. Signed-off-by: Samuel Holland <samuel@sholland.org>
Add the new option, function IDs, and prototypes for PSCI v1.1 implementations. In the process, fix some issues with the existing definitions: - Fix the incorrectly-named ARM_PSCI_0_2_FN64_SYSTEM_RESET2. - Replace the deprecated "affinity_level" naming with "power_level". Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
This adds a new PSCI implementation which communicates with SCP firmware running on the AR100 using the SCPI protocol. This allows it to support the full set of PSCI v1.1 features, including CPU idle states, system suspend, and multiple reset methods. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A10 SoC and all existing boards verbatim from the Linux v5.15 tag. While this update should not impact any existing U-Boot functionality, the changes to the USB PHY detection GPIO properties are needed to convert that driver to use the DM GPIO framework. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A20 SoC and all existing boards verbatim from the Linux v5.15 tag. An important change here is to the GMAC phy-mode property on several boards; this needs to be set correctly once the rtl8211e driver starts configuring the PHY RGMII delays from the devicetree. This update also includes changes to the USB PHY detection GPIO properties which are needed to convert that driver to use the DM GPIO framework. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16 SoCs and all existing boards verbatim from the Linux v5.15 tag. These SoCs are combined into one commit due to some interdependencies: - The unit addresses were removed from bitbanged I2C buses, which drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts and sun6i-a31-colombus.dts. - The pinctrl nodes were renamed, including some used by the shared sunxi-reference-design-tablet.dtsi. This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree. As with the other SoCs, updates of note are EMAC phy-mode changes to set RGMII delays, conversion of GPIO pull-up from pinconf to GPIO flags, and renaming the detection GPIO properties in the USB PHY nodes. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A80 SoC and all existing boards verbatim from the Linux v5.15 tag. This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A83T SoC and all existing boards verbatim from the Linux v5.15 tag. As with the other SoCs, updates of note are EMAC phy-mode changes to set RGMII delays, and adding detection GPIO properties in the USB PHY nodes. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the H2+/H3 SoCs and all existing boards verbatim from the Linux v5.15 tag. As with the other SoCs, updates of note are EMAC phy-mode changes to set RGMII delays. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards verbatim from the Linux v5.15 tag. This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree for the R40 SoC verbatim from the Linux v5.15 tag. None of the existing boards had any devicetree updates. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the A64 SoC and all existing boards verbatim from the Linux v5.15 tag. As with the other SoCs, updates of note are EMAC phy-mode changes to set RGMII delays. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the H5 SoC and all existing boards from the Linux v5.15 tag, with minor changes to account for the different directory layout for 64-bit SoCs. While there were some recent changes to the shared H3/H5 devicetree, the only H5-specific change is fixing the EMAC phy-mode in one board. Signed-off-by: Samuel Holland <samuel@sholland.org>
Copy the devicetree source for the H6 SoC and all existing boards verbatim from the Linux v5.15 tag. This update should not impact any existing U-Boot functionality. Series-to: sunxi Cover-letter: sunxi: Devicetree sync from Linux v5.15 This series brings all of our devicetrees up to date with the latest stable Linux version. << something about ABI compat >> Here is the list of new files which were not added by this sync: - sun4i-a10-topwise-a721.dts - sun50i-a100-allwinner-perf1.dts - sun50i-a100.dtsi - sun50i-h6-pine-h64-model-b.dts - sun5i-a13-licheepi-one.dts - sun5i-a13-pocketbook-touch-lux-3.dts - sun5i-gr8-evb.dts - sun7i-a20-linutronix-testbox-v2.dts - sun7i-a20-olinuxino-lime-emmc.dts - sun8i-a23-ippo-q8h-v1.2.dts - sun8i-a23-ippo-q8h-v5.dts - sun8i-a33-et-q8-v1.6.dts - sun8i-a33-ippo-q8h-v1.2.dts - sun8i-h3-nanopi-r1.dts - sun8i-r16-nintendo-nes-classic.dts - sun8i-r16-nintendo-super-nes-classic.dts - sun8i-r40-feta40i.dtsi - sun8i-r40-oka40i-c.dts - sun8i-s3-elimo-impetus.dtsi - sun8i-s3-elimo-initium.dts - sun8i-t3-cqa3t-bv3.dts - sun8i-v3-sl631-imx179.dts - sun8i-v3-sl631.dtsi END Signed-off-by: Samuel Holland <samuel@sholland.org>
Create a do-nothing driver for each sunxi pin controller variant. Since only one driver can automatically bind to a DT node, since the GPIO driver already requires a manual binding process, and since the pinctrl driver needs access to some of the same information, refactor the GPIO driver to be bound by the pinctrl driver. This commit should cause no functional change. Series-changes: 2 - Merge all SoC drivers into one file and one U_BOOT_DRIVER. - Add a consumer for the APB bus clock Signed-off-by: Samuel Holland <samuel@sholland.org>
# Conflicts: # arch/arm/mach-sunxi/Kconfig
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: TekkamanV <tekkamanv@163.com> [Samuel: Only kept the non-Fedora-specific subset of changes] Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: TekkamanV <tekkamanv@163.com> [Samuel: Kept default prompt, trimmed things to stay under 1 MiB] Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jisheng Zhang <jszhang@kernel.org> [Samuel: licheepi -> lichee; drop DRAM size; other changes] Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
If this value is not increased, the error occurs during loading uncompressed kernel from fitImage: "Error: inflate() returned -5 Image too large: increase CONFIG_SYS_BOOTM_LEN" Signed-off-by: Cezary Sobczak <cezary.sobczak@3mdeb.com>
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I just pushed a change to commonize some of the D1 configuration with the Allwinner ARM U-Boot port. So I applied your change on top of that as 301dc3a. Please let me know if that works for you. |
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@smaeul I checked it and it's working for me so I think you can close this PR. |
MartinHerren
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Raymond Mao <raymond.mao@linaro.org> says: Motivations for changes: Current SMBIOS library and command-line tool is not fully matching with the requirements: 1. Missing support for other mandatory types (smaeul#7, u-boot#9, u-boot#16, u-boot#17, u-boot#19). 2. Only a few platforms support SMBIOS node from the device tree. 3. Values of some fields are hardcoded in the library other than fetching from the device hardware. 4. Embedded data with dynamic length is not supported (E.g. Contained Object Handles in Type smaeul#2 and Contained Elements in Type smaeul#3) Changes: 1. Refactor the SMBIOS library and command-line tool to better align with the SMBIOS spec. 2. Create an arch-specific driver for all aarch64-based platforms to fetch SMBIOS private data from the device hardware (processor and cache). 3. Create a sysinfo driver to poppulate platform SMBIOS private data. 4. Add generic SMBIOS DTS file for arm64 platforms for those common strings and values which cannot be retrieved from the system registers. Vendors can create their own SMBIOS node using this as an example. For those boards without SMBIOS nodes, this DTS file can be included to have a generic SMBIOS information of the system. 5. Add support for Type smaeul#7 (Cache Information) and link its handles to Type smaeul#4. 6. To minimize size-growth for those platforms which have not sufficient ROM spaces or the platforms which don't need detailed SMBIOS information, new added fields are only being built when kconfig GENERATE_SMBIOS_TABLE_VERBOSE is selected. Once this patch is acceptted, subsequent patch sets will add other missing types (u-boot#9, u-boot#16, u-boot#17, u-boot#19). Tests: To test this with QEMU arm64, please follow the guide on dt_qemu.rst to get a merged DT to run with. ``` qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \ | dtc - -o merged.dtb qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \ -dtb merged.dtb ``` Link: https://lore.kernel.org/r/20241206225438.13866-1-raymond.mao@linaro.org
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Hello, during the integration of the Nezha U-Boot to the Yocto Project I ran into a bug during loading an uncompressed kernel image from
fitImage. You can find mymeta-nezhalayer here.If
CONFIG_SYS_BOOTM_LENvalue is not increased, the error occurs during loading uncompressed kernel fromfitImage:Signed-off-by: Cezary Sobczak cezary.sobczak@3mdeb.com