8000 smpaiagua (Sergio Paiagua) / Starred · GitHub
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  • Lawrence Berkeley National Laboratory

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"Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE

Python 19 6 Updated Nov 9, 2021

Verilator open-source SystemVerilog simulator and lint system

C++ 2,944 670 Updated Jun 12, 2025

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage …

C 31 10 Updated Oct 18, 2018

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage …

C 1 Updated Oct 18, 2018

A huge VHDL library for FPGA and digital ASIC development

VHDL 388 72 Updated Jun 14, 2025

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Verilog 60 14 Updated Jun 13, 2025
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