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Feature - Product/Quotient/Remainder (PQR) Instruction Class #498
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This was referenced Jul 26, 2023
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Codecov Report
@@ Coverage Diff @@
## main #498 +/- ##
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- Coverage 89.55% 89.30% -0.26%
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Files 23 23
Lines 10119 10283 +164
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+ Hits 9062 9183 +121
- Misses 1057 1100 +43
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We don't use the original BPF backend of LLVM, since we have a separate SBF backend https://github.com/solana-labs/llvm-project/tree/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF |
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There is still an ongoing discussion about if we want to keep sign extension: solana-labs/solana#32924 And we are still missing a test for all the deprecated features. But that will go into another PR. |
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This was referenced Jan 10, 2024
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Multiplications and divisions will get a new more uniform and versatile instruction encoding in SBPFv2.
Scheme of the instruction encoding:
01Instructions of the new
BPF_PQRclass:06/000001100E/0000111016/000101101E/0001111026/001001102E/0010111036/00110110BPF_UHMUL64_IMMuhmul64 dst, imm3E/00111110BPF_UHMUL64_REGuhmul64 dst, src46/01000110BPF_UDIV32_IMMudiv32 dst, imm34/BPF_DIV32_IMM/div32 dst, imm4E/01001110BPF_UDIV32_REGudiv32 dst, src3C/BPF_DIV32_REG/div32 dst, src56/01010110BPF_UDIV64_IMMudiv64 dst, imm37/BPF_DIV64_IMM/div64 dst, imm5E/01011110BPF_UDIV64_REGudiv64 dst, src3F/BPF_DIV64_REG/div64 dst, src66/01100110BPF_UREM32_IMMurem32 dst, imm94/BPF_MOD32_IMM/mod32 dst, imm6E/01101110BPF_UREM32_REGurem32 dst, src9C/BPF_MOD32_REG/mod32 dst, src76/01110110BPF_UREM64_IMMurem64 dst, imm97/BPF_MOD64_IMM/mod64 dst, imm7E/01111110BPF_UREM64_REGurem64 dst, src9F/BPF_MOD64_REG/mod64 dst, src86/10000110BPF_LMUL32_IMMlmul32 dst, imm24/BPF_MUL32_IMM/mul32 dst, imm8E/10001110BPF_LMUL32_REGlmul32 dst, src2C/BPF_MUL32_REG/mul32 dst, src96/10010110BPF_LMUL64_IMMlmul64 dst, imm27/BPF_MUL64_IMM/mul64 dst, imm9E/10011110BPF_LMUL64_REGlmul64 dst, src2F/BPF_MUL64_REG/mul64 dst, srcA6/10100110AE/10101110B6/10110110BPF_SHMUL64_IMMshmul64 dst, immBE/10111110BPF_SHMUL64_REGshmul64 dst, srcC6/11000110BPF_SDIV32_IMMsdiv32 dst, immCE/11001110BPF_SDIV32_REGsdiv32 dst, srcD6/11010110BPF_SDIV64_IMMsdiv64 dst, immDE/11011110BPF_SDIV64_REGsdiv64 dst, srcE6/11100110BPF_SREM32_IMMsrem32 dst, immEE/11101110BPF_SREM32_REGsrem32 dst, srcF6/11110110BPF_SREM64_IMMsrem64 dst, immFE/11111110BPF_SREM64_REGsrem64 dst, srcIn the LLVM backend, the instruction info needs to be adjusted here:
https://github.com/solana-labs/llvm-project/blob/7b8db05b564faffb522434b73b7082662171f94a/llvm/lib/Target/SBF/SBFInstrInfo.td#L311