nexys3MIPSSoC

A simple MIPS SoC implemented on Digilent Nexys3 board

Naming convention

// TODO

This project was released under GPLv3 License

Name		Name	Last commit message	Last commit date
Latest commit History 28 Commits
ipcore_dir		ipcore_dir
.gitignore		.gitignore
7_seg_Dev.v		7_seg_Dev.v
7seg_Dev_IO.v		7seg_Dev_IO.v
BTN_Anti_jitter.v		BTN_Anti_jitter.v
Coprocessor.v		Coprocessor.v
Counter_3channel.v		Counter_3channel.v
Counter_x.ngc		Counter_x.ngc
LICENSE		LICENSE
MIO_BUS.ngc		MIO_BUS.ngc
MIO_BUS.v		MIO_BUS.v
Muliti_cycle_Cpu.v		Muliti_cycle_Cpu.v
Nexys3_Master.ucf		Nexys3_Master.ucf
RAM_I_D.coe		RAM_I_D.coe
RAM_I_D_E.coe		RAM_I_D_E.coe
README.md		README.md
Regs.v		Regs.v
Top_Muliti_IOBUS.v		Top_Muliti_IOBUS.v
alu.v		alu.v
arbiter.v		arbiter.v
biu.v		biu.v
cellram_ctrl.v		cellram_ctrl.v
char_rom.coe		char_rom.coe
clk_div.v		clk_div.v
ctrl.v		ctrl.v
data_path.v		data_path.v
gpu.v		gpu.v
led_Dev_IO.ngc		led_Dev_IO.ngc
led_Dev_IO.v		led_Dev_IO.v
mux2to1_32.v		mux2to1_32.v
mux4to1_32.v		mux4to1_32.v
mux4to1_5.v		mux4to1_5.v
nexys3MIPSSoC.xise		nexys3MIPSSoC.xise
ps2.v		ps2.v
ps2_wb.v		ps2_wb.v
seven_seg_Dev_IO.ngc		seven_seg_Dev_IO.ngc
vcache.v		vcache.v
vga.v		vga.v
vgabase.v		vgabase.v
vgachar.v		vgachar.v
vgamem.v		vgamem.v