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verilog

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logisim-evolution

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Apr 27, 2025
Java

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Apr 28, 2025
Scala

openwifi

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Updated Apr 18, 2025
C

verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Apr 29, 2025
C++

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Apr 23, 2025
Assembly

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power

Updated Mar 24, 2021
Verilog

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

fpga core riscv verilog risc-v

Updated Apr 27, 2025
Verilog

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Nov 8, 2024
C

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

Updated Apr 28, 2025
Python

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Apr 28, 2025
Verilog

SpinalHDL / SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

Updated Apr 28, 2025
Scala

icestudio

FPGAwars / icestudio

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

Updated Apr 19, 2025
JavaScript

pConst / basic_verilog

Must-have verilog systemverilog modules

Updated Apr 8, 2025
Verilog

analogdevicesinc / hdl

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Apr 29, 2025
Verilog

serv

olofk / serv

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Mar 18, 2025
Verilog

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Apr 28, 2025
Haskell

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203

Updated Oct 9, 2024
Verilog

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Feb 26, 2025
Python

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

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