Tags: towoe/chisel
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Merge pull request chipsalliance#4277 from chipsalliance/cd/update-ci… …rct-from-firtool-1.76.0-to-firtool-1.77.0 [cd] Bump CIRCT from firtool-1.76.0 to firtool-1.77.0
Fix emitted FIRRTL for dynamic index of size 0 Vec (chipsalliance#4275)… … (chipsalliance#4276) This is currently a warning but not yet an error so we need to emit legal FIRRTL. (cherry picked from commit d5ccf48) Co-authored-by: Jack Koenig <koenig@sifive.com>
Add and use Mill wrapper script (backport chipsalliance#4119) (chipsa… …lliance#4125) * Add and use Mill wrapper script (chipsalliance#4119) This saves developers from having to install a dependency. It also allows us to drop an old Github Actions dependency that hasn't been updated in 2 years. This is the standard practice for projects using Mill on Github. (cherry picked from commit 0f2efb5) # Conflicts: # .github/workflows/test.yml # CONTRIBUTING.md # benchmark/src/main/scala/chisel3/benchmark/Benchmark.scala * Resolve backport conflicts --------- Co-authored-by: Jack Koenig <koenig@sifive.com>
Add and use Mill wrapper script (backport chipsalliance#4119) (chipsa… …lliance#4124) * Add and use Mill wrapper script (chipsalliance#4119) This saves developers from having to install a dependency. It also allows us to drop an old Github Actions dependency that hasn't been updated in 2 years. This is the standard practice for projects using Mill on Github. (cherry picked from commit 0f2efb5) # Conflicts: # .github/workflows/test.yml # CONTRIBUTING.md # benchmark/src/main/scala/chisel3/benchmark/Benchmark.scala * Resolve backport conflicts --------- Co-authored-by: Jack Koenig <koenig@sifive.com>
Remove extra bit from `SRAMInterface` address width (backport chipsal… …liance#3830) (chipsalliance#3839) * Remove extra bit from `SRAMInterface` address width (chipsalliance#3830) (cherry picked from commit 4f1f4a7) # Conflicts: # src/test/scala/chiselTests/util/SRAMSpec.scala * Resolve backport conflicts --------- Co-authored-by: Deborah Soung <debs@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
Provide require message for negative widths (backport chipsalliance#4008 ) (chipsalliance#4010) * Provide require message for negative widths (chipsalliance#4008) (cherry picked from commit 751a4cf) # Conflicts: # src/test/scala/chiselTests/UIntOps.scala * Resolve backport conflicts --------- Co-authored-by: Jack Koenig <koenig@sifive.com>
Fix ChiselStage and Builder handling of logging (backport chipsallian… …ce#3895) (chipsalliance#3898) * Fix ChiselStage and Builder handling of logging (chipsalliance#3895) Previously, object circt.stage.ChiselStage was ignoring the Logger. Also, Chisel was not creating its own logger scope which could lead to clobbering of the Console when running invoking Chisel in the same process multiple times. Fix various places we had to workaround this behavior and fix tests checking --log-level debug. (cherry picked from commit 88d147d) # Conflicts: # src/main/scala/circt/stage/ChiselStage.scala * Resolve backport conflicts * Make logger annotations unserializable Change logger annotations to mix-in the Unserializable trait so that they will not emitted by a stage. These annotations are not intended to be seen by CIRCT and these should be stripped from the output FIRRTL text. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> --------- Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add DataProduct for Iterables and primitive types (chipsalliance#3856)
Add Scala 2.13.13 to cross-build (chipsalliance#3851) (chipsalliance#… …3864) (cherry picked from commit 68eb248) Co-authored-by: Jack Koenig <koenig@sifive.com>
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