RISC-V V-extension 1.0 has been frozen for a while, but there is currently no serious open-source test suite available, and this project tries to fill that void.
The Spike simulator is known as the RISC-V gold standard simulator, and although we don't know how Spike is tested, it does fully support the V extension. So we added a custom special instruction to Spike, and for any test, let it automatically generate a reference result for that test. This way, we generate tests for all instructions almost automatically. Under this framework, all we have to do is write a simple config file for each instruction.
For starters, you can directly download the pre-generated tests from Github Action Artifacts.
- Add check mechanism for CSR register
- Add V register coverage test
- Add test coverage statistics
- Add negative tests
- Add tests for sub-extensions (e.g. Zvamo, Zvfh).
- Support Zve64f.
riscv64-unknown-elf-gccwith RVV 1.0 support- The Spike simulator
- Golang 1.19+
riscv-pkif you need to generate user-mode binaries
make -j$(nproc)
After make, you will find all the generated tests in out/v[vlen]x[xlen][mode]/bin/stage2/.
Options:
VLEN, default is 256XLEN, default is 64, we do not support specifying ELEN yet, ELEN is consistent with XLENMODE, default ismachine, can bemachine,virtualoruserINTEGER, default is 0, set to 1 if you don't want float tests (i.e. for Zve32x or Zve64x)PATTERN, default is.*, set to a valid regex to generate the tests of your interests (e.g.PATTERN='^v[ls].+\.v$'to generate load/store tests)TESTFLOAT3LEVEL, default is 2, must be one of 1 or 2, testing level for testfloat3 generated cases.TEST_MODE, default isself, set tocosimif you want to generate faster tests without self-verification (to be used with co-simulators).REPEAT, default is1, set to greater value to repeat the same V instruction n times for a better coverage (only valid for float instructions).
For example, to generate isa=rv32gcv varch=vlen:128,elen:32 mode=machine tests, use make -e VLEN=128 XLEN=32 MODE=machine -j$(nproc).
Note: single/single.go generates tests directly from stage 1, suitable for targets with co-simulators (or simply use
TEST_MODE=cosimif you're lazy).
This repository also provides a nix derivation with the following output provided:
${riscv-vector-test}/bin/*: Generator binaries${riscv-vector-test}/include/*: Necessary headers for runtime usage${riscv-vector-test}/configs/*: Necessary runtime configs
This project uses third-party projects, and the licenses of these projects are attached to the corresponding directories.
The code for this project is distributed under the MIT license.