#
Starred repositories
Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
Contains the code for the Flexus cycle-accurate simulator, used in QFlex.
Rigorous verification of APB AMBA5 with 400+ tests. Design and Verification documentations provided. A python script is used to run regression.
Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
A configurable synchronizer model for Dynamic CDC
This repository modifies the original riscv-formal framework to work with Synopsys VC Formal. It includes updates to scripts and configurations for formal verification of RISC-V cores, focusing sol…
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Formal Verification of NoC of ESP
Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb
在最短的时间里搭建 GEM5 FS + QEMU 平台，并构建能被二者共用的操作系统（默认 Ubuntu 16.04.5 server）及内核（默认 4.15.18）。
A collection of license features from a varity of EDA vendors
RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm
High quality and composable RTL libraries in SystemVerilog
ShanghaiTech Heterogeneous System-Level Cache Architecture
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
Aquila-MP: Multi-Core RISC-V Processor with Level-2 Cache Coherence & Atomic Operations
The goal of the LOROF project is to architect, design, verify, and validate a RISC-V RV32IMAC_Zicsr_Zifencei Sv32 Quad-Core Superscalar Out-of-Order Virtual-Memory-Supporting CPU, successfully boot…
XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
Implement a ChatGPT-like LLM in PyTorch from scratch, step by step
Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor