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Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.
PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
Microsoft BASIC for 6502 (Commodore, Apple, KIM-1, AIM-65, OSI, ...)
beneater / msbasic
Forked from mist64/msbasicMicrosoft BASIC for 6502 (Commodore, Apple, KIM-1, AIM-65, OSI, ...)
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…
The Linux Kernel Module Programming Guide (updated for 5.0+ kernels)
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Simple .INI file parser in C, good for embedded systems
🌊 Digital timing diagram rendering engine
Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
A simple example using a virtual serial port in Linux
Tests for all valid opcodes of the 6502 and 65C02 processor