#
Starred repositories
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
A directory of Western Digital’s RISC-V SweRV Cores
Lantern官方版本下载 蓝灯 翻墙 代理 科学上网 外网 加速器 梯子 路由 proxy vpn circumvention gfw
OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.
Hardware implementation of the SHA-256 cryptographic hash function
RISC-V Tools (ISA Simulator and Tests)
The root repo for lowRISC project and FPGA demos.
An open-source microcontroller system based on RISC-V
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Package manager and build abstraction tool for FPGA/ASIC development
This is the main repository for all the examples for the book Practical UVM
OpenDLA / OpenDLA
Forked from silicontalks01/OpenDLAA discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
xfguo / riscv-openwrt
Forked from openwrt/openwrtPorting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.