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Starred repositories

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Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Java 1 Updated Jun 21, 2020

A Vivado 2017.4 project that consists of a build to test the powlib crossbar on the Nexys DDR 4 board.

Verilog 2 Updated Feb 6, 2019
Shell 1 1 Updated Nov 29, 2019

通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs …

77 7 Updated May 24, 2020

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

VHDL 140 21 Updated Dec 8, 2019

The root repo for lowRISC project and FPGA demos.

SystemVerilog 602 150 Updated Aug 3, 2023

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,729 1,036 Updated Mar 24, 2021
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