8000 xiguo1030 (Xiaorang Guo) / Starred · GitHub
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  • TU Munich
  • Garching near Munich

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Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

Verilog 149 29 Updated Dec 13, 2020
Go 6 1 Updated May 12, 2025

Fully connected dense neural network in SystemVerilog, synthesisable to an FPGA for neural network computation acceleration

SystemVerilog 5 1 Updated Mar 15, 2023
Jupyter Notebook 4 Updated Nov 15, 2023

RISCV model for Verilator/FPGA targets

C 53 19 Updated Oct 17, 2019

A quantum control architecures simulator.

C++ 9 2 Updated Jan 4, 2020

Rocket Chip Generator

Scala 3,477 1,168 Updated May 27, 2025
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