8000 1211562881 / Starred · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content
View 1211562881's full-sized avatar

Block or report 1211562881

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results
MATLAB 435 98 Updated May 27, 2024

Open source eGPU dock for ROG Ally and ROG Flow

C 524 50 Updated May 4, 2025

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Verilog 1,401 313 Updated Apr 21, 2025

Universal utility for programming FPGA

C++ 1,365 296 Updated Jul 2, 2025

Change part number or package in a Xilinx 7-series FPGA bitstream

C 39 13 Updated Apr 27, 2020

An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。

Verilog 181 37 Updated Sep 15, 2023

Linux kernel source tree

C 196,815 56,776 Updated Jul 2, 2025

你管这破玩意叫操作系统源码 — 像小说一样品读 Linux 0.11 核心代码

HTML 21,185 2,845 Updated Mar 22, 2025

PCI express simulation framework for Cocotb

Python 168 53 Updated Apr 30, 2025

cocotb: Python-based chip (RTL) verification

Python 2,020 559 Updated Jul 2, 2025

SonicBOOM: The Berkeley Out-of-Order Machine

Scala 1,928 459 Updated May 6, 2025

NetFPGA 1G infrastructure and gateware

Verilog 377 140 Updated Apr 11, 2019

32-bit Superscalar RISC-V CPU

Verilog 1,049 179 Updated Sep 18, 2021

a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog

Verilog 23 5 Updated Jul 20, 2023

RDMA core userspace libraries and daemons

C 1,844 756 Updated Jul 1, 2025

【冲破内核瓶颈,让I/O性能飙升】DPDK工程师手册,官方文档,最新视频,开源项目,实战案例,论文,大厂内部ppt,知名工程师一览表

1,397 473 Updated May 20, 2024

Various caches written in Verilog-HDL

Verilog 125 41 Updated Apr 24, 2015

Open source FPGA-based NIC and platform for in-network compute

Verilog 1,927 465 Updated Jul 5, 2024

The RIFFA development repository

Verilog 838 331 Updated Jun 11, 2024

Personal warehouse

Verilog 2 Updated Nov 27, 2019

RV64I CPU

Verilog 3 Updated Jul 18, 2021

A automated simulation script for Modelsim. Write by Python and Tcl

Python 4 Updated Sep 26, 2021

一个志在实现STM32F1、F2和F4工程模板的项目,集成了FreeRTOS、LWIP、FATFS、DSP、USB、IAP、菜单库、有限状态机模板等等的组件,以及未来将加入的加密、BPNN、最小二乘、音频图片视频解码、LittlevGL等诸多常用的算法或组件,并具有良好的易用性、解耦性和可剪裁性!

C 372 79 Updated Apr 12, 2023

Generator Bootcamp Material: Learn Chisel the Right Way

Jupyter Notebook 1,048 294 Updated Sep 10, 2024
0