Stars
MESIF cache coherency protocol for the GEM5 simulator
A collection of Ascon implementations & documents (as submodules)
Ascon - Lightweight Authenticated Encryption & Hashing
NIST LWC Hardware Reference Implementation of Ascon v1.2
Verilog AXI stream components for FPGA implementation
AXI DMA Check: A utility to measure DMA speeds in simulation
Xilinx Embedded Software (embeddedsw) Development
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
Vector processor for RISC-V vector ISA
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
General Purpose AXI Direct Memory Access
Hardware, Linux Driver and Library for the Zynq AXI DMA interface
Embedded 32-bit RISC uProcessor with SDRAM Controller
Fixed Point Math Library for Verilog
Verilog AXI components for FPGA implementation
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform