This repo contains the Yocto Linux environment for the 360nosc0pe project which tries to build an open source oscilloscope FPGA design and software for Xilinx Zynq based oscilloscopes like the Siglent SDS 1x0xX-E series.
Supported machines:
- Siglent SDS1202X-E
- Siglent SDS1104X-E or SDS1204X-E (exact same hardware)
Right now we only support JTAG booting. A way to boot from USB and leave the stock firmware untouched is planned but not yet implemented.
As userspace we use Arch Linux ARM which makes it easy to install packages on the system when developing. In theory you can use whatever userspace you want. Even the one Yocto could build for you.
The project is in a relatively early development stage. So far we completed the following tasks:
- Reverse engineering of most of the pinout
- Get Linux booting
- Get all usual peripherals working like USB, Ethernet, serial port etc.
- Get a framebuffer working for the display
- Establish SPI communication with the devices in the signal path
- Build FPGA cores for the frontpanel input
- Write some auxiliary linux drivers for the frontpanel LEDs, power management IC etc.
- Build an FPGA core which performs the offset DAC multiplexing
- Implement a SERDES receiver to receive samples from the ADCs
Things that are left to do:
- Draw schematics of the frontend etc. to get proper documentation and even more overview about the hardware
- Input driver for the front panel buttons and encoders
- Trigger system
- A bunch of triggers (maybe exchangeable by using partial reconfiguration on the FPGA)
- Measurements on waveforms (Frequency, Voltage etc.)
- Waveform rendering in hardware with intensity grading
- Bus analyzers in software or hardware
- Proper python API to control the scope in a useful manner for automated tasks
- Scope UI + software
- Reverse engineering of the MSO dongle of the 4ch scope
- Create a USB boot chain - the stock u-boot tried to load stuff from USB already, we need to reload the bitstream, reconfigure PLLs etc.
If you want a quick start tutorial and just copy some stuff into your terminal to build everything, check out this tutorial
If you want to help us bringing this project forward, you are invited to do so. You can send us pull-requests on github if you have patches that you want to submit.
If you want to reach us, you can do so in the #siglenthax channel on the Freenode IRC channel.
You need a Linux installation with Xilinx Vivado to build the FPGA bitstream and all necessary dependencies for Yocto.
We offer a docker container which contains all of this here.
Every time you need to specify a machine, you can choose from these targets:
| Name | Machine name |
|---|---|
| Siglent SDS1202X-E | sds1202xe |
| Siglent SDS1104X-E | sds1104xe |
Build the FPGA hardware definition and bitstream in the fpga repo:
./generate_bitstreams.sh <machine>
Setup the yocto environment in yocto:
MACHINE=<machine> DISTRO=scope source scripts/setup-environment build
Edit conf/local.conf to change the following lines to match the location of your .hdf file generated by Vivado. If you are running this in our docker container, you don't need to do anything.
XILINX_SDK_TOOLCHAIN ?= "/opt/Xilinx/SDK/${XILINX_VER_MAIN}"
HDF_BASE ?= "file://"
HDF_PATH ?= "${BSPDIR}/../fpga/${MACHINE}.hdf"
Build everything including the root filesystem:
bitbake scope-image-dev
Build only the necessary boot components:
bitbake virtual/kernel kernel-modules virtual/bootloader virtual/ps7-tcl-init virtual/bitstream device-tree
To load the Bitstream, configure the SoC and run u-boot, run
xsdb -eval 'source scripts/jtag_load.tcl'
from within the docker container after building everything.
If you set the jumper on the board to JTAG boot, u-boot will try to load a kernel and device tree from a TFTP server after getting a DHCP lease.
You can use the scripts/run_dnsmasq.sh script to run a dnsmasq server and configure NAT for the target if you need to. The root filesystem comes from an NFS share by default. You need to set one up by yourself.
NOTE: both scripts need to know things like which machine you are targeting or the names of your network interfaces. You can edit this in the scripts itself. Feel free to come up with a better solution!
If you change something in the Zynq block in Vivado it might be necessary to regenerate the hardware defintion to generate a new register init sequence for the Zynq.
To get the new init code, perform the following steps:
- Build the bitstream/hardware definition
- Rebuild your yocto targets. The changed hardware definition should be picked up automatically.