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  • University of Electronic Science and Technology of China
  • Shenzhen, China
  • 08:36 (UTC +08:00)

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Showing results
13 Updated May 23, 2025

A high-efficiency hybrid solving CEC algorithm

C 11 1 Updated May 25, 2023
C++ 3 1 Updated May 28, 2025

Must-have verilog systemverilog modules

Verilog 1,785 404 Updated Apr 8, 2025

Implementations of DeepPlace, PRNet, HubRouter, PreRoutGNN and FlexPlanner.

Raku 239 52 Updated Nov 26, 2024

Awesome Artificial Intelligence for Electronic Design Automation Papers.

171 18 Updated Dec 28, 2023

formal verification tools in VLSI industry

9 Updated Mar 7, 2018

Collection of digital hardware modules & projects (benchmarks)

Verilog 59 11 Updated May 7, 2025

Mulberry, an o1-like Reasoning and Reflection MLLM Implemented via Collective MCTS

Python 1,185 109 Updated Mar 28, 2025

A wrapper around kissat to support push/pop (performance would be bad)

C++ 3 Updated Dec 23, 2024

Hardware Formal Verification Tool

Rust 52 11 Updated May 29, 2025

A fork of the Kissat SAT solver with additional features. Supports incremental solving.

C 14 Updated Aug 13, 2022

An advanced SAT solver

C++ 856 195 Updated May 25, 2025

CaDiCaL SAT Solver

C++ 448 150 Updated May 26, 2025

Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays and uninterpreted functions and their combinations. Its name …

SMT 254 41 Updated May 24, 2025

benchmarks for hls equivalence checking

VHDL 8 1 Updated Nov 22, 2022

Open source high performance IEEE-754 floating unit

Scala 72 26 Updated Feb 26, 2024

Verilog auto debug with Gpts

Verilog 5 4 Updated Feb 25, 2025

LLM Evaluation Benchmark on Hardware Formal Verification

Python 21 2 Updated Apr 3, 2025
C 535 100 Updated Mar 17, 2025

A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.

SMT 348 67 Updated Aug 23, 2024

Checks the equivalence between AIGs using BDDs

C++ 6 Updated Jul 10, 2023

AIGER And-Inverter-Graph Library

C 78 25 Updated May 27, 2025
Python 9 Updated Sep 29, 2024

ABC: System for Sequential Logic Synthesis and Formal Verification

C 995 631 Updated May 26, 2025

EPFL logic synthesis benchmarks

Verilog 192 38 Updated May 19, 2025

Recent papers related to hardware formal verification.

70 9 Updated Sep 20, 2023

SeaHorn Verification Framework

C 451 131 Updated May 27, 2025
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