8000 daxzio repositories · GitHub
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    • Spack's community package recipes
      Python
      191000Updated Jul 17, 2025Jul 17, 2025
    • spack

      Public
      A flexible package manager that supports multiple versions, configurations, platforms, and compilers.
      Python
      2.4k000Updated Jul 16, 2025Jul 16, 2025
    • Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
      Python
      49000Updated Jul 16, 2025Jul 16, 2025
    • Cocotb AHB Extension - AHB VIP
      Python
      9000Updated Jul 16, 2025Jul 16, 2025
    • GNU toolchain for RISC-V, including GCC
      C
      1.3k000Updated Jul 16, 2025Jul 16, 2025
    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      973000Updated Jul 16, 2025Jul 16, 2025
    • cocotb

      Public
      cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
      Python
      564000Updated Jul 14, 2025Jul 14, 2025
    • sby

      Public
      SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
      Python
      83000Updated Jul 8, 2025Jul 8, 2025
    • Verilog
      1300Updated Jul 6, 2025Jul 6, 2025
    • Verilog
      25000Updated Jul 5, 2025Jul 5, 2025
    • Verilog
      1300Updated Jul 4, 2025Jul 4, 2025
    • VexRiscv

      Public
      A FPGA friendly 32 bit RISC-V CPU implementation
      Assembly
      459000Updated Jul 4, 2025Jul 4, 2025
    • Git mirror of Gaisler's GRLIB/LEON3/LEON5/NOELV releases
      VHDL
      8000Updated Jul 4, 2025Jul 4, 2025
    • Extension to the built-in ast module. Finds comments in source code and adds them to the parsed tree.
      Python
      10000Updated Jun 29, 2025Jun 29, 2025
    • pyfpga

      Public
      A Python package to use FPGA development tools programmatically.
      Python
      15000Updated Jun 19, 2025Jun 19, 2025
    • < 10000 div class="Description-module__container--b3n6F">Fork of OpenOCD that has RISC-V support
      C
      354000Updated Jun 18, 2025Jun 18, 2025
  • axi_mem2p

    Public
    Verilog
    0000Updated Jun 17, 2025Jun 17, 2025
  • Verilog UART
    Verilog
    140000Updated Jun 17, 2025Jun 17, 2025
  • Verilog
    0000Updated Jun 17, 2025Jun 17, 2025
  • UART models for cocotb
    Python
    22000Updated Jun 11, 2025Jun 11, 2025
  • SystemRDL 2.0 language compiler front-end
    C++
    74000Updated Jun 9, 2025Jun 9, 2025
  • VeeR EL2 Core
    SystemVerilog
    88000Updated Jun 3, 2025Jun 3, 2025
  • PeakRDL

    Public
    Control and status register code generator toolchain
    Python
    29000Updated May 23, 2025May 23, 2025
  • FlooNoC

    Public
    A Fast, Low-Overhead On-chip Network
    SystemVerilog
    40000Updated May 19, 2025May 19, 2025
  • I2C models for cocotb
    Python
    15000Updated Apr 22, 2025Apr 22, 2025
  • Python
    13000Updated Apr 19, 2025Apr 19, 2025
  • myhdl

    Public
    The MyHDL development repository
    Python
    252000Updated Apr 10, 2025Apr 10, 2025
  • qspiflash

    Public
    0000Updated Mar 25, 2025Mar 25, 2025
  • Verilog AXI stream components for FPGA implementation
    Python
    248000Updated Feb 28, 2025Feb 28, 2025
  • Verilog I2C interface for FPGA implementation
    Verilog
    184000Updated Feb 28, 2025Feb 28, 2025
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