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    61 repositories

    • spack

      Public
      A flexible package manager that supports multiple versions, configurations, platforms, and compilers.
      Python
      •
      Other
      •2.4k•0•0•0•Updated May 16, 2025May 16, 2025

    • PeakRDL-regblock

      Public
      Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
      Python
      •
      GNU General Public License v3.0
      •46•0•0•0•Updated May 16, 2025May 16, 2025

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •942•0•0•0•Updated May 15, 2025May 15, 2025

    • riscv-gnu-toolchain

      Public
      GNU toolchain for RISC-V, including GCC
      C
      •
      Other
      •1.2k•0•0•0•Updated May 15, 2025May 15, 2025

    • cocotb

      Public
      cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •550•0•0•0•Updated May 14, 2025May 14, 2025

    • sby

      Public
      SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
      Python
      •
      Other
      •80•0•0•0•Updated May 14, 2025May 14, 2025

    • pyfpga

      Public
      A Python package to use FPGA development tools programmatically.
      Python
      •
      GNU General Public License v3.0
      •15•0•0•0•Updated May 12, 2025May 12, 2025

    • cocotbext-jtag

      Public
      Verilog
      •1•3•0•0•Updated May 11, 2025May 11, 2025

    • PeakRDL

      Public
      Control and status register code generator toolchain
      Python
      •
      GNU General Public License v3.0
      •28•0•0•0•Updated May 2, 2025May 2, 2025

    • Cores-VeeR-EL2

      Public
      VeeR EL2 Core
      SystemVerilog
      •
      Apache License 2.0
      •82•0•0•0•Updated Apr 28, 2025Apr 28, 2025

    • VexRiscv

      Public
      A FPGA friendly 32 bit RISC-V CPU implementation
      Assembly
      •
      MIT License
      •444•0•0•0•Updated Apr 23, 2025Apr 23, 2025

    • cocotbext-i2c

      Public
      I2C models for cocotb
      Python
      •
      MIT License
      •13•0•0•0•Updated Apr 22, 2025Apr 22, 2025

    • cocotbext-spi

      Public
      Python
      •
      MIT License
      •13•0•0•0•Updated Apr 19, 2025Apr 19, 2025

    • riscv-openocd

      Public
      Fork of OpenOCD that has RISC-V support
      C
      •
      Other
      •347•0•0•0•Updated Apr 16, 2025Apr 16, 2025

    • myhdl

      Public
      The MyHDL development repository
      Python
      •
      GNU Lesser General Public License v2.1
      •251•0•0•0•Updated Apr 10, 2025Apr 10, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •37•0•0•0•Updated Apr 9, 2025Apr 9, 2025

    • grlib-gpl-mirror

      Public
      Git mirror of Gaisler's GRLIB/LEON3/LEON5/NOELV releases
      VHDL
      •8•0•0•0•Updated Mar 28, 2025Mar 28, 2025

    • cocotbext-apb

      Public
      Verilog
      •1•2•0•0•Updated Mar 27, 2025Mar 27, 2025

    • qspiflash

      Public
      0•0•0•0•Updated Mar 25, 2025Mar 25, 2025

    • verilog-axis

      Public
      Verilog AXI stream components for FPGA implementation
      Python
      •
      MIT License
      •247•0•0•0•Updated Feb 28, 2025Feb 28, 2025

    • verilog-i2c

      Public
      Verilog I2C interface for FPGA implementation
      Verilog
      •
      MIT License
      •182•0•0•0•Updated Feb 28, 2025Feb 28, 2025

    • verilog-uart

      Public
      Verilog UART
      Verilog
      •
      MIT License
      •136•0•0•0•Updated Feb 28, 2025Feb 28, 2025

    • verilog-axi

      Public
      Verilog AXI components for FPGA implementation
      Verilog
      •
      MIT License
      •483•0•0•0•Updated Feb 28, 2025Feb 28, 2025

    • verilog-lfsr

      Public
      Fully parametrizable combinatorial parallel LFSR/CRC module
      Python
      •
      MIT License
      •58•0•0•0•Updated Feb 27, 2025Feb 27, 2025

    • rocket-chip

      Public
      Rocket Chip Generator
      Scala
      •
      Other
      •1.2k•0•0•0•Updated Jan 30, 2025Jan 30, 2025

    • cocotbext-dvi

      Public
      Verilog
      •
      MIT License
      •0•0•0•0•Updated Jan 27, 2025Jan 27, 2025

    • cocotbext-ahb

      Public
      Cocotb AHB Extension - AHB VIP
      Python
      •
      MIT License
      •9•0•0•0•Updated Jan 25, 2025Jan 25, 2025

    • picorv32

      Public
      PicoRV32 - A Size-Optimized RISC-V CPU
      Verilog
      •
      ISC License
      •822•0•0•0•Updated Jan 8, 2025Jan 8, 2025

    • site-myhdl

      Public
      myhdl.org website
      HTML
      •10•0•0•0•Updated Jan 7, 2025Jan 7, 2025

    • VeeRwolf

      Public
      FuseSoC-based SoC for SweRV EH1
      Verilog
      •71•0•0•0•Updated Jan 7, 2025Jan 7, 2025
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