GitHub - andres-alcala-gutier/mips-architecture: Simplified MIPS Processor Architecture - Instruction Set Architecture (ISA): ADD, SUB, MULT, DIV, AND, OR, SLT, ADDI, ANDI, ORI, SLTI, LW, SW, BEQ, BNE and J

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Simplified MIPS Processor Architecture - Instruction Set Architecture (ISA): ADD, SUB, MULT, DIV, AND, OR, SLT, ADDI, ANDI, ORI, SLTI, LW, SW, BEQ, BNE and J

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU.v		ALU.v
ALUControl.v		ALUControl.v
ANDGate.v		ANDGate.v
Add4.v		Add4.v
Adder.v		Adder.v
Control.v		Control.v
DataMemory.v		DataMemory.v
EXMEM.v		EXMEM.v
IDEX.v		IDEX.v
IFID.v		IFID.v
InstructionMemory.v		InstructionMemory.v
MEMWB.v		MEMWB.v
MIPS.v		MIPS.v
MIPS_tb.v		MIPS_tb.v
Mux28.v		Mux28.v
Mux32.v		Mux32.v
Mux5.v		Mux5.v
PC.v		PC.v
Registers.v		Registers.v
ShiftLeft26.v		ShiftLeft26.v
ShiftLeft32.v		ShiftLeft32.v
SignExtend.v		SignExtend.v
_MIPSnoBuffers.png		_MIPSnoBuffers.png

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Simplified MIPS Processor Architecture - Instruction Set Architecture (ISA): ADD, SUB, MULT, DIV, AND, OR, SLT, ADDI, ANDI, ORI, SLTI, LW, SW, BEQ, BNE and J

verilog 32-bits mips-architecture