GitHub - andrew-castle/mips-architecture: Computer Architecture

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.v		ALU.v
ALUControl.v		ALUControl.v
ANDGate.v		ANDGate.v
Add4.v		Add4.v
Adder.v		Adder.v
Control.v		Control.v
DataInit.list		DataInit.list
DataMemory.v		DataMemory.v
EXMEM.v		EXMEM.v
IDEX.v		IDEX.v
IFID.v		IFID.v
InstructionMemory.v		InstructionMemory.v
MEMWB.v		MEMWB.v
MIPS.v		MIPS.v
MIPS_tb.v		MIPS_tb.v
Mux28.v		Mux28.v
Mux32.v		Mux32.v
Mux5.v		Mux5.v
PC.v		PC.v
Registers.v		Registers.v
ShiftLeft26.v		ShiftLeft26.v
ShiftLeft32.v		ShiftLeft32.v
SignExtend.v		SignExtend.v

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