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VirtualSatellite4-Core Public
Forked from virtualsatellite/VirtualSatellite4-CoreVirtual Satellite Core - Baseline Framework and IDE Tools
Java Eclipse Public License 2.0 UpdatedApr 21, 2022 -
verilog-pcie Public
Forked from alexforencich/verilog-pcieVerilog PCI express components
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MBSE-ve Public
Forked from Open-MBEE/exec-veWeb Client Application designed to enable users to interact with Model Based System Engineering (MBSE) models
JavaScript Apache License 2.0 UpdatedApr 19, 2022 -
corundum Public
Forked from corundum/corundumOpen source FPGA-based NIC and platform for in-network compute
Verilog Other UpdatedApr 8, 2022 -
litepcie Public
Forked from enjoy-digital/litepcieSmall footprint and configurable PCIe core
Verilog Other UpdatedApr 7, 2022 -
verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedMar 30, 2022 -
cocotbext-pcie Public
Forked from alexforencich/cocotbext-pciePCI express simulation framework for Cocotb
Python MIT License UpdatedMar 16, 2022 -
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cocotbext-axi Public
Forked from alexforencich/cocotbext-axiAXI interface modules for Cocotb
Python MIT License UpdatedMar 4, 2022 -
spi-master Public
Forked from nandland/spi-masterSPI Master for FPGA - VHDL and Verilog
VHDL MIT License UpdatedJan 31, 2022 -
verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedDec 28, 2021 -
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riffa Public
Forked from KastnerRG/riffaThe RIFFA development repository
Verilog Other UpdatedJun 24, 2021 -
JSONinSV Public
Forked from zhouchuanrui/JSONinSVJSON lib in Systemverilog
SystemVerilog MIT License UpdatedMar 28, 2021 -
Yarr-fw Public
Forked from Yarr/Yarr-fwFirmware repository for the PCIe FPGA cards used for the YARR system
VHDL GNU General Public License v3.0 UpdatedFeb 19, 2021 -
bluespecpcie Public
Forked from sangwoojun/bluespecpciePCIe library for the Xilinx 7 series FPGAs in the Bluespec language
Bluespec UpdatedFeb 4, 2021 -
fpga-drive-aximm-pcie Public
Forked from fpgadeveloper/fpga-drive-aximm-pcieExample designs for FPGA Drive FMC
Tcl MIT License UpdatedFeb 1, 2021 -
fpga-pcie-dma-jpeg-encoder Public
Forked from torukskywalker/fpga-pcie-dma-jpeg-encoderUpdatedJan 11, 2021 -
serial_port_plotter Public
Forked from CieNTi/serial_port_plotterDisplays real time data from serial port
C++ GNU General Public License v3.0 UpdatedDec 2, 2020 -
fpga-source Public
Forked from myriadrf/xtrx-fpga-sourceThe source code for the XTRX FPGA image
Verilog Other UpdatedOct 29, 2020 -
Artix-Express-35 Public
Forked from OfficialNT/Artix-Express-35This is a base design for an Artix-7 35T based FPGA card with PCIE and USB interface. This is meant as an open source, DIY alternative to certain commercial PCIE FPGA development cards.
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abc Public
Forked from berkeley-abc/abcABC: System for Sequential Logic Synthesis and Formal Verification
C Other UpdatedAug 13, 2020 -
vscode Public
Forked from microsoft/vscodeVisual Studio Code
TypeScript MIT License UpdatedAug 3, 2020 -
verible Public
Forked from chipsalliance/veribleVerible provides a SystemVerilog parser, style-linter, and formatter.
C++ Apache License 2.0 UpdatedJul 31, 2020 -
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OpenFPGA Public
Forked from lnis-uofu/OpenFPGAAn Open-source FPGA IP Generator
C MIT License UpdatedJul 28, 2020 -
OpenSTA Public
Forked from The-OpenROAD-Project/OpenSTAOpenSTA engine
C++ GNU General Public License v3.0 UpdatedJul 27, 2020 -
Surelog Public
Forked from chipsalliance/SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API.
C++ Apache License 2.0 UpdatedJul 26, 2020
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