Stars
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
hardware（scopefun 双通道虚拟示波器，基于 Kicad 的 PCB 工程）
Scopefun FPGA source code（scopefun 双通道虚拟示波器，FPGA 底层实现）
include hdlc (miao), 422 grapher, 1553b
development interface mil-std-1553b for system on chip
A simulator for 1553B protocol, based on BU-61580 protocol card
PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
Example designs for FPGA Drive FMC
Contains VHDL implementing an 8085, Holt HI-6130 1553 IC, and Memory. Also includes firmware used to demo the system.
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
YosysHQ / abc
Forked from berkeley-abc/abcABC: System for Sequential Logic Synthesis and Formal Verification
Style guide enforcement for VHDL
This is a tool to check various rules of a digital design written in verilog HDL. This tool uses Icarus Verilog APIs
Repurposing existing HDL tools to help writing better code
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Example LED blinking project for your FPGA dev board of choice
A High-performance Timing Analysis Tool for VLSI Systems