Tags: dingiso/riscv-crypto
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spec: scalar adoc work around wavedrom issue. - replace encoding fields with a '0' string since they were just showing up empty before. Need to investigate for next release On branch master Your branch is up-to-date with 'origin/master'. Changes to be committed: modified: doc/scalar/insns/aes32dsi.adoc modified: doc/scalar/insns/aes32dsmi.adoc modified: doc/scalar/insns/aes32esi.adoc modified: doc/scalar/insns/aes32esmi.adoc modified: doc/scalar/insns/aes64ds.adoc modified: doc/scalar/insns/aes64dsm.adoc modified: doc/scalar/insns/aes64es.adoc modified: doc/scalar/insns/aes64esm.adoc modified: doc/scalar/insns/aes64im.adoc modified: doc/scalar/insns/aes64ks1i.adoc modified: doc/scalar/insns/aes64ks2.adoc modified: doc/scalar/insns/sha256sig0.adoc modified: doc/scalar/insns/sha256sig1.adoc modified: doc/scalar/insns/sha256sum0.adoc modified: doc/scalar/insns/sha256sum1.adoc modified: doc/scalar/insns/sha512sig0.adoc modified: doc/scalar/insns/sha512sig0h.adoc modified: doc/scalar/insns/sha512sig0l.adoc modified: doc/scalar/insns/sha512sig1.adoc modified: doc/scalar/insns/sha512sig1h.adoc modified: doc/scalar/insns/sha512sig1l.adoc modified: doc/scalar/insns/sha512sum0.adoc modified: doc/scalar/insns/sha512sum0r.adoc modified: doc/scalar/insns/sha512sum1.adoc modified: doc/scalar/insns/sha512sum1r.adoc modified: doc/scalar/insns/sm3p0.adoc modified: doc/scalar/insns/sm3p1.adoc modified: doc/scalar/insns/sm4ed.adoc modified: doc/scalar/insns/sm4ks.adoc Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (untracked content) modified: extern/riscv-opcodes (modified content) modified: extern/sail-riscv (untracked content)
spec-scalar: Remove "draft" ready for v0.9.0 release On branch master Your branch is up-to-date with 'origin/master'. Changes to be committed: modified: doc/riscv-crypto-spec-scalar.tex Changes not staged for commit: modified: extern/riscv-compliance (modified content) modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content, untracked content) Untracked files: doc/supp/entropy-source-bd.png doc/supp/entropy-source-verification.adoc
spec,spike,sail,toolchain: Update SM4/RV32 AES encodings. After feedback (see riscv#65) and discussion within the TG at the Dec 17'th 2020 meeting, the SM4 and RV32 AES instruction encodings have been changed to source rd from rs1, and re-use the rd field as encoding space. This was deemed preferable to reclaiming the opcode space with the former rd==rs1 scheme. The change updates the encodings in the specificaiton, and brings the other components of the repository in line with this: - Spike - Binutils - SAIL - Benchmarks - Intrinsics On branch dev/next-release Your branch is up-to-date with 'origin/dev/next-release'. Changes to be committed: modified: benchmarks/aes/zscrypto_rv32/aes_128_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_192_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_256_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_dec.S modified: benchmarks/aes/zscrypto_rv32/aes_enc.S modified: benchmarks/share/riscv-crypto-intrinsics.h modified: bin/better_parse_opcodes.py modified: doc/Makefile modified: doc/riscv-crypto-spec-scalar.tex modified: doc/tex/appx-scalar-encodings.tex modified: doc/tex/sec-scalar-aes.tex modified: doc/tex/sec-scalar-sha2.tex modified: doc/tex/sec-scalar-sm4.tex modified: sail/riscv_insts_crypto.sail modified: sail/riscv_insts_crypto_rv32.sail modified: sail/riscv_insts_crypto_rv64.sail modified: tools/opcodes-crypto-scalar-both modified: tools/opcodes-crypto-scalar-rv32 modified: tools/patch-binutils.patch modified: tools/patch-spike.patch Changes not staged for commit: modified: extern/riscv-compliance (modified content) modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content) modified: extern/sail-riscv (modified content, untracked content)
Merge branch 'master' into dev/next-release Fixed Conflicts: benchmarks/config/rv64-zscrypto.conf tools/patch-binutils.patch tools/patch-spike.patch Please enter the commit message for your changes. Lines starting with '#' will be ignored, and an empty message aborts the commit. On branch dev/next-release Your branch is up-to-date with 'origin/dev/next-release'. All conflicts fixed but you are still merging. Changes to be committed: modified: README.md modified: bin/parse_opcodes.py modified: doc/tex/sec-entropy-source.tex modified: sail/riscv_crypto_entropy_source.sail modified: tools/README.md new file: tools/gcc-patch-tasks.adoc modified: tools/patch-binutils.patch Changes not staged for commit: modified: extern/riscv-compliance (modified content) modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content) modified: extern/sail-riscv (modified content, untracked content)
spec: riscv#58 - more clarity on scalar feature group descriptions. On branch dev/next-release Your branch is up-to-date with 'origin/dev/next-release'. Changes to be committed: modified: doc/tex/sec-scalar-profiles.tex modified: doc/tex/sec-scalar-timing.tex Changes not staged for commit: modified: extern/riscv-compliance (modified content) modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content) modified: extern/riscv-opcodes (modified content) modified: extern/sail-riscv (modified content, untracked content)
Implement instruction re-naming. - Closes riscv#48 - Instruction Renaming - Closes riscv#46 - Shorter names, and consistency for instructions with immediate operands - Closes riscv#45 - Vector instruction names and dot-extensions - Closes riscv#42 - Use of "dots" in assembly instruction names - Closes riscv#41 - Change scalar instruction names to remove 's' prefix. This is a squash commit. It contains all of the commits made on the `dev/instruction-renaming` branch. --- commit 93be8b0 Author: Ben Marshall <ben.marshall@bristol.ac.uk> Date: Tue Sep 22 13:49:29 2020 +0100 sail: pollentropy -> pollentropyi commit 519a04f Author: Ben Marshall <ben.marshall@bristol.ac.uk> Date: Tue Sep 22 13:45:56 2020 +0100 spec, sail: Instruction renaming. - Implement all renaming for SAIL and LaTeX source file. On branch dev/instruction-renaming Changes to be committed: modified: doc/opcodes-crypto-scalar.tex modified: doc/opcodes-crypto-vector.tex modified: doc/tex/sec-scalar-aes.tex modified: doc/tex/sec-scalar-sha2.tex modified: doc/tex/sec-scalar-sm3.tex modified: doc/tex/sec-scalar-sm4.tex modified: doc/tex/sec-scalar.tex modified: doc/tex/sec-vector-aes.tex modified: doc/tex/sec-vector-grev.tex modified: doc/tex/sec-vector-rotate.tex modified: doc/tex/sec-vector-sha2.tex modified: sail/riscv_insts_crypto.sail modified: sail/riscv_insts_crypto_rv32.sail modified: sail/riscv_insts_crypto_rv64.sail modified: sail/riscv_types_crypto.sail modified: tools/opcodes-crypto-vector Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content) commit 5fa3fb1 Author: Ben Marshall <ben.marshall@bristol.ac.uk> Date: Sun Sep 20 18:55:22 2020 +0100 Working on riscv#48 - Instruction Renaming. - Renamed all scalar instructions in: - Benchmarks - Spike - Binutils - Opcode descriptions. - Still do do: - Specs: Vector and Scalar - SAIL code. - Example RTL. On branch dev/instruction-renaming Changes to be committed: modified: benchmarks/aes/zscrypto_rv32/aes_128_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_192_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_256_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_dec.S modified: benchmarks/aes/zscrypto_rv32/aes_enc.S modified: benchmarks/aes/zscrypto_rv64/aes_128_ks.S modified: benchmarks/aes/zscrypto_rv64/aes_192_ks.S modified: benchmarks/aes/zscrypto_rv64/aes_256_ks.S modified: benchmarks/aes/zscrypto_rv64/aes_dec.S modified: benchmarks/aes/zscrypto_rv64/aes_enc.S modified: benchmarks/aes/zscrypto_rv64/aes_ks_dec_invmc.S modified: benchmarks/sha256/zscrypto/sha256.c modified: benchmarks/sha512/zscrypto_rv64/sha512.c modified: benchmarks/share/riscv-crypto-intrinsics.h modified: benchmarks/sm4/zscrypto/sm4_zscrypto.c modified: tools/opcodes-crypto-scalar modified: tools/opcodes-crypto-vector modified: tools/patch-binutils.patch modified: tools/patch-spike.patch Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content, untracked content) modified: extern/riscv-isa-sim (modified content) On branch dev/next-release Your branch is up-to-date with 'origin/dev/next-release'. Changes to be committed: modified: benchmarks/aes/zscrypto_rv32/aes_128_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_192_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_256_ks.S modified: benchmarks/aes/zscrypto_rv32/aes_dec.S modified: benchmarks/aes/zscrypto_rv32/aes_enc.S modified: benchmarks/aes/zscrypto_rv64/aes_128_ks.S modified: benchmarks/aes/zscrypto_rv64/aes_192_ks.S modified: benchmarks/aes/zscrypto_rv64/aes_256_ks.S modified: benchmarks/aes/zscrypto_rv64/aes_dec.S modified: benchmarks/aes/zscrypto_rv64/aes_enc.S modified: benchmarks/aes/zscrypto_rv64/aes_ks_dec_invmc.S modified: benchmarks/sha256/zscrypto/sha256.c modified: benchmarks/sha512/zscrypto_rv64/sha512.c modified: benchmarks/share/riscv-crypto-intrinsics.h modified: benchmarks/sm4/zscrypto/sm4_zscrypto.c modified: doc/opcodes-crypto-scalar.tex modified: doc/opcodes-crypto-vector.tex modified: doc/tex/sec-scalar-aes.tex modified: doc/tex/sec-scalar-sha2.tex modified: doc/tex/sec-scalar-sm3.tex modified: doc/tex/sec-scalar-sm4.tex modified: doc/tex/sec-scalar.tex modified: doc/tex/sec-vector-aes.tex modified: doc/tex/sec-vector-grev.tex modified: doc/tex/sec-vector-rotate.tex modified: doc/tex/sec-vector-sha2.tex modified: sail/riscv_insts_crypto.sail modified: sail/riscv_insts_crypto_rv32.sail modified: sail/riscv_insts_crypto_rv64.sail modified: sail/riscv_types_crypto.sail modified: tools/opcodes-crypto-scalar modified: tools/opcodes-crypto-vector modified: tools/patch-binutils.patch modified: tools/patch-spike.patch Changes not staged for commit: modified: extern/riscv-gnu-toolchain (modified content) modified: extern/riscv-isa-sim (modified content)
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