8000 dpetrisko (Dan Petrisko) / Starred · GitHub
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BlackParrot on Zynq

SystemVerilog 43 17 Updated Mar 5, 2025

3-stage RV32IMACZb* processor with debug

Verilog 885 63 Updated Jun 20, 2025

An open-source static random access memory (SRAM) compiler.

Python 918 227 Updated Jun 30, 2025

fakeram generator for use by researchers who do not have acc 58ED ess to commercial ram generators

Python 37 16 Updated Jan 13, 2023

A Linux-capable RISC-V multicore for and by the world

SystemVerilog 710 191 Updated Apr 30, 2025

SystemVerilog to Verilog conversion

Haskell 643 59 Updated Jun 23, 2025

BaseJump STL: A Standard Template Library for SystemVerilog

SystemVerilog 584 107 Updated Jun 12, 2025

A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core

Verilog 12 Updated May 24, 2019

The OpenPiton Platform

Assembly 714 240 Updated May 20, 2025
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