#vcnn - verilog CNN
Verilog modules to build convolutional neural network on PYNQ FPGA.
Implemented:
- Multiply Accumulate (cnn1l) custom IP - built using Xilinx Floating Point Operator IP with custom state machine to perform depth wise pixel convolution operation from BRAMs. Also performs ReLU activation.
Unimplemented:
- Max Pool layer
- Average Pool layer
Contributors:
- Caio Motta - Building and training CNN model on Tensor Flow
- Barath Kumar Ramaswami - Training CNN model on Tensor Flow
- Gokul Prasath Nallasami - Building Hardware (Verilog) modules for implementing the trained CNN model.