Vigna is a CPU core that implements RISC-V Instruction Set. Current supported architecture is RV32I/E[M]
Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website
The current version is v1.21
This version is tested with riscv-tests, dhrystone and coremark.
If you find a bug or have any questions, you can create an issue.
Various contributions are welcomed!
- Features and Typical Applications
- Files in this Repository
- Memory Interface
- Design Details
- Future Plans
Vigna is a two-stage micro-controller style CPU with parallele state-machine architecture. The core has an approximate CPI of 3 when the instruction bus and data bus are separated. The micro-controller is size-optimized and has a simple extensible bus.
This core can be integrated into other systems and used as an auxiliary core on a FPGA. Due to the small size and low logic payload, it can be easily adapted into various systems.
This core has a ultra-low size on FPGAs. On Xilinx Artix-7 series FPGAs, it only uses 582 LUTs and 285FFs(Synthesized with Xilinx Vivado 2020.1 with default synthesis strategy).
You are reading it right now.
This Verilog file contains module vigna, which is the design rtl code of the core.
This Verilog file contains module vigna_top, which is a wrapper of vigna core.
This Verilog file defines the configurations of core vigna.
This directory contains MISC files for adaptions on different platforms. Design files including gpio and AXI4-Lite adapters are in this directory.
This Verilog file contains a module that adapts current bus into an AXI4-Lite bus interface. This adapter can be used with module vigna or vigna_top.
This Verilog file contains a module that merge 2 bus interfaces into one. This module uses a simple RS-latch logic. It is possible that warnings mignt occure when using linters like verilator or when synthesizing using yosys, but it should workout fine on FPGAs. If it turned out to be an error that cannot be solved, try fixing this by replacing the RS-latch logic with primitives.
A bus routing module that decide which way the bus signals should go with the accessing address. This module is recommanded to connect multiple slave devices and MMIOs.
GPIOs based on the native bus.
Module to get cycles(in 64-bits) after reset.
The uart module for a 2-wire uart interface with a simple fifo buffer.
The memory interface is basically the same with picorv32. The interface is a simple valid-ready interface that can run one memory transfer at a time:
output valid,
input ready,
output [31:0] addr,
input [31:0] rdata,
output [31:0] wdata,
output [ 3:0] wstrb
The core initiates a memory transfer by asserting valid. The valid signal stays high until the peer asserts ready. All core outputs are stable over the valid period. The transacton is done when both valid and ready are high. When the transaction is done, the core pulls valid down, and the peer should pull ready down as soon as it finds valid down.
In a read transfer wstrb must has the value 0 and wdata is unused.
The memory reads the address addr and makes the read value available on rdata in the cycle ready is high.
There is no need for an external wait cycle. The memory read can be implemented asynchronously with ready going high in the same cycle as valid.
In a write transfer wstrb is not 0 and rdata is unused. The memory write the data at wdata to the address addr and acknowledges the transfer by asserting ready.
The 4 bits of wstrb are write enables for the four bytes in the addressed
word. Only the 4 values 0000, 1111, 0011, 0001 are possible, i.e. no write, write 32 bits,
write lower 16 bits, or write a single byte.
There is no need for an external wait cycle. The memory can acknowledge the
write immediately with ready going high in the same cycle as valid.
For more examples and explainations, goto wiki.
See the wiki for details in the design.
Next: more documentation about design details.