The Hardisc is a 32-bit RISC-V IP core for use in safety/mission-critical environments, where random hardware faults, like bit flips caused by soft errors, are a concern. The core contains an in-order 6-stage pipeline with AMBA 3 AHB-Lite instruction/data bus interfaces.
The Hardisc's protection is based on a selective replication of resources inside the execution pipeline, complemented by ECCs and bus-interface protection. It provides fault-tolerance with minimal area and power consumtion overhead when compared to industry-standard Dual-Core Lockstep (DCLS) systems.
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More information about the protection, as well as results from the fault-injection experiments and physical synthesis, can be found in the open-access research article: Lockstep Replacement: Fault-Tolerant Design
The Hardisc was tested with the riscv-dv random instruction generator, and the log files were compared with the RISC-V Spike golden model. The verification environment and scripts will be added to the repository soon.
We highly appreciate your intention to improve the Hardisc. If you want to contribute, create your branch to commit your changes and open a Pull Request. If you have questions about the architecture or want to discuss improvements, please create a new thread in the Discussions tab.
If you find any bug or a hole in the protection (also considered a bug), please create a new Issue report.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).