10000 ricted98 (Riccardo Tedeschi) / Starred · GitHub
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RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

SystemVerilog 80 31 Updated Jun 9, 2025

Yosys Open SYnthesis Suite

C++ 3,860 959 Updated Jun 10, 2025

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Assembly 2,498 779 Updated Jun 9, 2025

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Verilog 264 68 Updated Jun 10, 2025
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