A simple processor designed using Verilog and Altera DE1 development board.
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Apr 22, 2020 - Verilog
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A simple processor designed using Verilog and Altera DE1 development board.
A simple sram controller and test for the altera DE1 FPGA board
⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
Academic projects created using Assembly, in the Intel FPGA Monitor Program, for the laboratory work done while attending the McGill Course ECSE 324 Computer Organization
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
Pin file in .qsf format for Altera DE1 FPGA
Synthesize a general purpose microprocessor (GPM) using verilog hdl code on Altera DE1 development board. The processor was used to find the greatest common divisor (GCD) between two integers.
Using finite state machine (FSM) approach to design a traffic light controller on Altera DE1 development board.
The Snake Game Made in VHDL for Altera DE1 using Quartus V.13
Kitchen-timer on Altera DE1 FPGA development kit - VHDL
Helps with Cross compilation for arm-gnueabihf-gcc linux compilation for the HPS found in cyclone V subsystems on DE1-SOC boards.
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
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