dual-issue

Here are 3 public repositories matching this topic...

dominiksalvet / super-riscv

Superscalar dual-issue RISC-V processor

open-source pipeline core rtl forwarding systemverilog gtkwave testbench superscalar in-order risc-v microarchitecture low-power verilator ahb3-lite instruction-level-parallelism dual-issue riscv-gcc

Updated Apr 28, 2025
SystemVerilog

Ellen7ions / Gemini

Star

pipeline mips cache dual-issue

Updated Mar 16, 2024
Verilog

dannydyl / SONY-Cell-SPU-Processor

Star

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

processor simd verilog computer-architecture vlsi cpu-architecture rtl-design dual-issue

Updated May 6, 2025
Verilog

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