Code, documentation, schematics, notes for my Ben Eater inspired breadboard computer and emulator
An implementation of a simple processor (SAP1) using VHDL
A FPGA implementation of Ben Eater's SAP-1 computer using the Digilent's BASYS 3 board.
Simple As Possible 1 Simulation. The circuit design is done by Proteus 8.1
SAP-1, or Simple As Possible-1, is a basic microprocessor designed for educational purposes by Albert Paul Malvino and Taiachi Shinano. It includes essential components like the instruction register, program counter, memory unit, and arithmetic logic unit, offering insight into computer architecture and digital logic in a simplistic manner.
A simulation of a Simple-As-Possible (SAP) computer, implemented in Logisim Evolution.
Modificação do SAP-01 com algumas instruções a mais, além de um terminal de display de instruções, feito pela plataforma LOGISIM.
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