A High-performance Timing Analysis Tool for VLSI Systems
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Linux generic dhcp snooping daemon using nflog and ebtables or nftables
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…
SensorThings work at DataCove
State Tag Application in Vue.js
OGC Location Building Blocks for SensorThings API
This repository encompasses all aspects of Hardware ASIC design, From RTL to GDS II, including Verilog, Synth, PD and Signoff (STA, PDN, etc.)
This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.
Silicon Highway Technologies Free STA, ASTA Timing Engine
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