Author: Yunhao Zhou
Date: 2024-11-08
Date: 2024-11-08
import Verilog_utils
verilog_obj = Verilog_utils.Verilog_Processor('<Verilog Design Dir>')class Verilog_Processor:
def __init__(self, design_dir=None, filter_out_tb=True, log_file='Verilog_Processor.log'):
self.design_dir = design_dir
self.file_list = search_files_recursively(design_dir, '.v')
if filter_out_tb:
self.file_list = filter_out_tb_files(self.file_list)
self.verilog_code = verilog_extractor_from_file_list(self.file_list)
self.module_dict = module_dict_extractor(self.verilog_code)
self.top_module_candidates, self.top_module_clk = find_top_module_and_clk_from_module_dict(self.module_dict)
self.log(log_file)
def log(self, log_path):
self.log = open(log_path, 'a')
content_dict = {'design_dir': self.design_dir, 'file_list': self.file_list, 'top_module_candidates': self.top_module_candidates, 'top_module_clk': self.top_module_clk}
self.log.write(json.dumps(content_dict) + '\n')
self.log.flush()
self.log.close()