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axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedMar 20, 2024 -
corundum Public
Forked from corundum/corundumOpen source FPGA-based NIC and platform for in-network compute
Verilog Other UpdatedDec 20, 2023 -
riffa Public
Forked from KastnerRG/riffaThe RIFFA development repository
Verilog Other UpdatedSep 28, 2023 -
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verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedApr 2, 2023 -
Chinese-Translation-of-PCI-Express-Technology- Public
Forked from ljgibbslf/Chinese-Translation-of-PCI-Express-Technology-Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare
MIT License UpdatedMar 27, 2023 -
ethernet-fmc-axi-eth Public
Forked from fpgadeveloper/ethernet-fmc-axi-ethExample design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
Tcl MIT License UpdatedDec 8, 2022 -
yuu_ahb Public
Forked from seabeam/yuu_ahbUVM AHB VIP
SystemVerilog MIT License UpdatedAug 1, 2022 -
Cosmos-plus-OpenSSD Public
Forked from Cosmos-OpenSSD/Cosmos-plus-OpenSSDCosmos OpenSSD + Hardware and Software source distribution
VHDL GNU General Public License v3.0 UpdatedJul 29, 2022 -
AXI-Ethernet-UVM Public
Forked from kkenshin1/AXI-Ethernet-UVMA Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
SystemVerilog MIT License UpdatedJun 1, 2022 -
axis_udp Public
Forked from alknvl/axis_udpThis repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 1…
Verilog MIT License UpdatedMar 15, 2022 -
awesome-dv Public
Forked from troyguo/awesome-dvAwesome ASIC design verification
UpdatedFeb 9, 2022 -
hbird-sdk Public
Forked from riscv-mcu/hbird-sdkOpenSource HummingBird RISC-V Software Development Kit
C Apache License 2.0 UpdatedJan 17, 2022 -
e203_hbirdv2 Public
Forked from riscv-mcu/e203_hbirdv2The Ultra-Low Power RISC-V Core
Verilog Apache License 2.0 UpdatedDec 21, 2021 -
linux-xlnx Public
Forked from Xilinx/linux-xlnxThe official Linux kernel from Xilinx
C Other UpdatedSep 3, 2021 -
ML-For-Beginners Public
Forked from microsoft/ML-For-Beginners12 weeks, 24 lessons, classic Machine Learning for all
Jupyter Notebook MIT License UpdatedJul 4, 2021 -
e200_opensource Public
Forked from SI-RISCV/e200_opensourceDeprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Verilog Apache License 2.0 UpdatedMar 24, 2021 -
Practical-UVM-IEEE-Edition Public
Forked from Practical-UVM-Step-By-Step/Practical-UVM-IEEE-EditionThis is the repository for the IEEE version of the book
Verilog UpdatedSep 29, 2020 -
ucore Public
Forked from kiukotsu/ucore清华大学操作系统课程实验 (OS Kernel Labs)
C GNU General Public License v2.0 UpdatedAug 30, 2020 -
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PYNQ_softmax Public
Forked from 9334swjtu/PYNQ_softmaxachieve softmax in PYNQ with heterogeneous computing.
VHDL UpdatedNov 1, 2018 -
ethernet_10ge_mac_SV_UVM_tb Public
Forked from andres-mancera/ethernet_10ge_mac_SV_UVM_tbSystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
Verilog UpdatedJul 16, 2018 -
ISP_UVM Public
Forked from nelsoncsc/ISP_UVMA Framework for Design and Verification of Image Processing Applications using UVM
SystemVerilog MIT License UpdatedNov 27, 2017 -
Cosmos-OpenSSD Public
Forked from Cosmos-OpenSSD/Cosmos-OpenSSDVerilog GNU General Public License v3.0 UpdatedSep 27, 2017 -
SDRAM-Verification Public
Forked from yvnr4you/SDRAM-VerificationThis is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by Dinesh in Opencores.org
Verilog UpdatedMar 26, 2017
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