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Starred repositories
RISC-V Formal Verification Framework
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A minimal GPU design in Verilog to learn how GPUs work from the ground up
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
RISC-V microcontroller IP core developed in Verilog
uBlock Origin - An efficient blocker for Chromium and Firefox. Fast and lean.
A brief computer graphics / rendering course
Use ripgrep to find TODO tags and display the results in a tree view
🖥️ Show current CPU usage, memory usage and net speed on panel
A GNOME Shell extenesion to hide Universal Access icon from the status bar
A live viewer for reMarkable written in PyQt5
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
Chrome extension to return youtube dislikes
Verilator open-source SystemVerilog simulator and lint system
🌊 Digital timing diagram rendering engine
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Reference manual for ForwardCom instruction set and software standards
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA